Multiplier Pipelining Functional Description

For 3200DX, MX, SX, SX-A and eX the multiplier architecture does not allow you to select the latency of the pipelined multiplier or the number of logic levels between the pipeline stages. Registers are automatically inserted between the major components of the architecture, primarily the multiplexor and adder cores, as shown in the following figure.

Figure 10-32. Booth Multiplier Architecture

The number of pipeline stages is a function of the width of the DataB input. The number of logic levels per pipeline stage is a function of the width of the DataA input. Therefore, the number of logic levels per pipeline stage is equal to the number of logic levels of the first adder (WIDTHA + 1) plus 1 for the 4 to 1 multiplexor, as shown in the Figure 10-32figure.

Table 10-109. Pipeline Stages as a Function of WidthB
WidthB Range	Pipeline Stages
2	0
3-4	1
5-8	2
9-16	3

Table 10-110. Logic Levels per Pipeline Stage as a Function of WidthA
WidthA Range	Logic Levels
2-5	3
6-17	4
18-29	5

For more information on the Fast Carry-Chain cores available with the Axcelerator family, please refer to Fast Carry Chains (Axcelerator® only).