57.35 SSC Electrical Specifications

Figure 57-43. SSC Transmitter, TK and TF in Output Timing Diagrams

Figure 57-44. SSC Transmitter, TK in Input, and TF in Output Timing Diagrams

Figure 57-45. SSC Transmitter, TK in Output, and TF in Input Timing Diagrams

Figure 57-46. SSC Transmitter, TK and TF in Input Timing Diagrams

Figure 57-47. SSC Receiver, RK and RF in Input Timing Diagrams

Figure 57-48. SSC Receiver, RK in Input and RF in Output Timing Diagrams

Figure 57-49. SSC Receiver, RK and RF in Output Timing Diagrams

Figure 57-50. SSC Receiver, RK in Output and RF in Input Timing Diagrams

Table 57-48. Synchronous Serial Controller Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDIO=VDDIN 2.5V to 3.6V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
Transmitter
SSC_0	TKOUTTFOUT	TK edge to TF/TD (TK output, TF output)	-1.059	—	4.446	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_1	TKINTFOUT	TK edge to TF/TD (TK input, TF output)	3.566	—	12.76	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_2	TKOTFSTIME	TF setup time before TK edge (TK output)	11.046	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_3	TKOTFHTIME	TF hold time after TK edge (TK output)	0	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_4	TKOUTTFIN	TK edge to TF/TD (TK output, TF input)	-1.677	—	3.754	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_4	TKOUTTFIN	TK edge to TF/TD (TK output, TF input)	-1.677 + (2 × tCPMCK)	—	3.754 + (2 × tCPMCK)	ns	VDDIO = 3.3V, CLOAD = 30 pF, STTDLY = 0 START = 4, 5 or 7 Refer to note 2 for tCPMCK
SSC_5	TKITFSTIME	TF setup time before TK edge (TK input)	0	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_6	TKITFHTIME	TF hold time after TK edge (TK input)	tCPMCK	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF Refer to note 2 for tCPMCK
SSC_7	TKINTFIN	TK edge to TF/TD (TK input, TF input)	3.567	—	12.009	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_7	TKINTFIN	TK edge to TF/TD (TK input, TF input)	3.567 + (3 × tCPMCK)	—	12.009 + (3 × tCPMCK)	ns	VDDIO = 3.3V, CLOAD = 30 pF, STTDLY = 0 START = 4, 5 or 7 Refer to note 2 for tCPMCK
Receiver
SSC_8	RKIRFRDISTIME	RF/RD setup time before RK edge (RK input)	0	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_9	RKIRFRDHTIME	RF/RD hold time after RK edge (RK input)	tCPMCK	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF Refer to note 2 for tCPMCK
SSC_10	RKINDELAY	RK edge to RF (RK input)	3.433	—	10.667	ns	VDDIO = 3.3V, CLOAD = 30 pF
SSC_11	RKORFRDSTIME	RF/RD setup time before RK edge (RK output)	9.035 - tCPMCK	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF Refer to note 2 for tCPMCK
SSC_12	RKORFRDHTIME	RF/RD hold time after RK edge (RK output)	tCPMCK - 3.351	—	—	ns	VDDIO = 3.3V, CLOAD = 30 pF Refer to note 2 for tCPMCK
SSC_13	RKOUTDELAY	RK edge to RF (RK output)	-0.102	—	3.347	ns	VDDIO = 3.3V, CLOAD = 30 pF
Note: For output signals (TF, TD, RF), minimum and maximum access times are defined. The minimum access time is the time between the TK (or RK) edge and the signal change. The maximum access timing is the time between the TK edge and the signal stabilization. tCPMCK is MCK period.

PIC32CZ CA70/MC70

57.35 SSC Electrical Specifications