57.33 HSMCI Electrical Specifications
| AC CHARACTERISTICS | Standard
Operating Conditions: VDDIO = VDDIN 2.5V to 3.6V (unless otherwise
stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | ||||||
|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
| SD/SDIO Default Speed Mode | |||||||
| SD_5 | tSDCK | Clock Frequency | — | — | 25 | MHz | — |
| SD_7 | tDUTY | Duty Cycle | — | 50 | — | % | — |
| SD_9 | tHIGH | Clock High Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_11 | tLOW | Clock Low Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_13 | tRISE | Clock Rise Time | DI_25 | ns | DI_25: Refer to the I/O Electrical Specifications | ||
| SD_15 | tFALL | Clock Fall Time | DI_27 | ns | DI_27: Refer to the I/O Electrical Specifications | ||
| SD_17 | tIN_SETUP | Input Setup Time | 5 | — | — | ns | — |
| SD_19 | tIN_HOLD | Input Hold Time | 5 | — | — | ns | — |
| SD_21 | tOUT_DLY | Output Delay Time | — | — | 14 | ns | VDDIO = 3.3V, CLOAD = 30 pF |
| SD_23 | tOUT_SETUP | Output HOLD Time | 0 | — | — | ns | |
| SD/SDIO High-Speed Mode | |||||||
| SD_25 | tSDCK | Clock Frequency | — | — | 50 | MHz | — |
| SD_27 | tDUTY | Duty Cycle | — | 50 | — | % | — |
| SD_29 | tHIGH | Clock High Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_30 | tLOW | Clock Low Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_31 | tRISE | Clock Rise Time | DI_25 | ns | DI_25: Refer to the I/O Electrical Specifications | ||
| SD_32 | tFALL | Clock Fall Time | DI_27 | ns | DI_27: Refer to the I/O Electrical Specifications | ||
| SD_33 | tIN_SETUP | Input Setup Time | 6 | — | — | ns | — |
| SD_35 | tIN_HOLD | Input Hold Time | 2 | — | — | ns | — |
| SD_37 | tOUT_DLY | Output Delay Time | — | — | 14 | ns | VDDIO = 3.3V, CLOAD = 30 pF |
| SD_39 | tOUT_SETUP | Output Hold Time | 2.5 | — | — | ns | |
| MMC Default-Speed Mode | |||||||
| SD_41 | tSDCK | Clock Frequency | — | — | 26 | MHz | — |
| SD_43 | tDUTY | Duty Cycle | — | 50 | — | % | — |
| SD_45 | tHIGH | Clock High Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_47 | tLOW | Clock Low Time | (1000/(2*tSDCK))-0.5(tRISE+tFALL) | — | — | ns | — |
| SD_49 | tRISE | Clock Rise Time | DI_25 | ns | DI_25: Refer to the I/O Electrical Specifications | ||
| SD_51 | tFALL | Clock Fall Time | DI_27 | ns | DI_27: Refer to the I/O Electrical Specifications | ||
| SD_53 | tIN_SETUP | Input Setup Time | 3 | — | — | ns | — |
| SD_55 | tIN_HOLD | Input Hold Time | 3 | — | — | ns | — |
| SD_57 | tOUT_DLY | Output Delay Time | — | — | 11.7 | ns | VDDIO = 3.3V, CLOAD = 30 pF |
| SD_59 | tOUT_SETUP | Output Hold Time | 8.3 | — | — | ns | |
|
Note:
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