57.18 DAC Module Electrical Specifications
| AC CHARACTERISTICS | Standard
Operating Conditions: VDDIN 2.5V to 3.6V (unless otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial | |||||||
|---|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions | |
| Reference Range, Timing and Accuracy | ||||||||
| DAC_1 | DRES | DAC Resolution | — | — | 12 | Bits | — | |
| DAC_3 | DCLK | Internal DAC Clock Frequency | — | — | 12 | MHz | VDDIN(min) | |
| DAC_5 | DSAMP | DAC Sampling Rate | Low-Power mode (DACC_ACR.IBCTLCHx = 1) | — | — | 0.5 | MSPS | +/-4 LSB of final value for step size ≤ 100 LSB at CLOAD and RLOAD w/VDDIN = 3.3V |
| High-Power mode (DACC_ACR.IBCTLCHx = 3) | — | — | 1 | MSPS | ||||
| DAC_7 | VOUT | Output Voltage Linear Range (DACC_ACR.IBCTLCHx = 3) | GNDANA + 0.5% × VREFP | — | 99% × VREFP | V | VREFP = VDDIN Code = 0x000 to 0xFFF No RLOAD CLOAD = 50 pF | |
| DAC_9 | VREFP(1) | DAC Reference Input Voltage | VDDIN(min) or ≥ 2.5V whichever is greater | — | VDDIN | V | — | |
| DAC_11 | CLOAD | DAC Out maximum load to meet VOUT and TSET | — | — | 50 | pF | — | |
| DAC_13 | RLOAD | DAC Out maximum load to meet VOUT and TSET | 5 | — | — | kΩ | — | |
| DAC_15 | Tset | DAC Settling Time (DACC_ACR.IBCTLCHx = 3) | — | 0.5 | 2.5 | µs | DACC_CDRx(n-1) to DACC_CDRx(n) ±0.5 LSB at CLOAD and RLOAD w/ VDDIN = 3.3V | |
| DAC_17 | Tset_FS | DAC Full Scale Settling Time (DACC_ACR.IBCTLCHx = 3) | — | 1 | 1.2 | µs | DACC_CDRx = 0x000 to DACC_CDRx = 0xFFF at CLOAD and RLOAD w/ VDDIN = 3.3V | |
| DAC_20 | Rout | DAC output resistor 0.3V < Vout < VDDIN -0.3V DACC_ACR.IBCTLCHx = 3 | — | 15 | — | Ω | VDDIN = 3.3V at RLOAD | |
| DAC output resistor Vout > VDDIN -0.3V DACC_ACR.IBCTLCHx = 3 | — | 550 | — | VDDIN = 3.3V at RLOAD | ||||
| DAC output resistor Vout < 0.3V DACC_ACR.IBCTLCHx = 3 | — | 550 | — | VDDIN = 3.3V at RLOAD | ||||
| DAC output resistor Vout = VREFP/2 DACC_ACR.IBCTLCHx = 0 (Bypass mode, buffer off) | — | 300 | — | kΩ | VDDIN = 3.3V at No RLOAD | |||
| SINGLE ENDED MODE (2) | ||||||||
| SDAC_19 | INL | Integral Non Linearity (DACC_ACR.IBCTLCHx = 3) | -10 | +/-2 | 10 | LSB | VREFP = VDDIN = 3.3V w/ CLOAD and No RLOAD | |
| SDAC_21 | DNL | Differential Non Linearity (DACC_ACR.IBCTLCHx = 3) | -4 | +/-2 | 4 | LSB | ||
| SDAC_23 | GERR | Gain Error (DACC_ACR.IBCTLCHx = 3) | -41 | — | 41 | LSB | VREFP = VDDIN = 3.3V w/ CLOAD and No RLOAD | |
| SDAC_25 | EOFF(3) | Offset Error | -9 | — | 9 | LSB | VREFP = VDDIN = 3.3V w/ CLOAD and No RLOAD | |
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Note:
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