57.13 XOSC Electrical Specifications

Table 57-15. External XTAL and Clock Electrical Specifications(1)
AC CHARACTERISTICSStandard Operating Conditions: VDDPLLUSB = 2.5V to 3.6V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
XOSC_1FOSC_XOSCXOSC Crystal Frequency3—20MHzEnabled by CKGR_MOR.MOSCXTEN = 1 XIN, XOUT Primary Osc
XOSC_1ATOSCTOSC = 1/FOSC_XOSC333—50nsSee parameter XOSC_1 for FOSC_XOSC value
XOSC_2XOSC_ST (2)XOSC Crystal Start-up Time ——160000TOSCCrystal stabilization time only not Oscillator Ready
XOSC_3CXINXOSC XIN parasitic pin capacitance—7.2—pF—
XOSC_5CXOUTXOSC XOUT parasitic pin capacitance—7.2—pF—
XOSC_11CLOAD (3) Crystal load capacitance FOSC = 3 MHz——18pFCrystal ESR ≤ 150Ω
XOSC_13 Crystal load capacitance FOSC = 8 MHz——18pFCrystal ESR ≤140Ω
XOSC_15 Crystal load capacitance FOSC = 12 MHz——12pFCrystal ESR ≤ 120Ω
XOSC_17 Crystal load capacitance FOSC = 16 MHz——12pFCrystal ESR ≤ 80Ω
XOSC_19 Crystal load capacitance FOSC = 20 MHz——12pFCrystal ESR ≤ 50Ω
XOSC_33DLEVELMCU Crystal Osc Power Drive Level——100µW—
XOSC_35FOSC_XCLKExt Clock Oscillator Input Freq (XIN pin)——20MHzCKGR_MOR.MOSCXTEN = 0
XOSC_37XCLK_DCExt Clock Oscillator (XIN) Duty Cycle405060%CKGR_MOR.MOSCXTEN = 0
XOSC_39XCLK_FSTPrimary XIN Clock Fail Safe Time-out Period (5)2*8*1/FOSC_XOSCµs—
Note:
  1. VDDPLLUSB = VDDIO = VDDIN = 3.3V.
  2. This is for guidance only. A major component of crystal start-up time is based on the 2nd party crystal MFG parasitics that are outside the scope of this specification. If this is a major concern the customer would need to characterize this based on their design choices.
  3. Crystal load capacitor calculation is as follows:
    • Standard PCB trace capacitance = 1.5 pf per 12.5 mm (0.5 inches) (i.e., PCB STD TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
    • XTAL PCB capacitance typical therefore ~= 2.5 pf for a tight XTAL PCB layout
    • For CXIN and CXOUT within 4 pf of each other, assume CXTAL_EFF = ((CXIN+CXOUT) / 2)
      Note: Averaging CXIN and CXOUT will effect final calculated CLOAD value by less than 0.25 pF.

    Equation 1:

    MFG CLOAD Spec = {( [CXIN + C1] * [CXOUT + C2] ) / [CXIN + C1 + C2 + CXOUT] } + estimated oscillator PCB stray capacitance

    • Assuming C1 = C2 and CXin ~= CXout, the formula can be further simplified and restated to solve for C1 and C2 by:

    Equation 2: (i.e., Simplified Equation #1)

    C1 = C2 = ((2 * MFG Cload spec) - CXTAL_EFF - (2 * PCB capacitance))

    For example,

    • XTAL Mfg CLOAD Data Sheet Spec = 18 pF
    • XTAL PCB trace Capacitance = 2.5 pF
    • CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF, therefore CXTAL_EFF = ((CXIN+CXOUT) / 2)

      CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF

      C1 = C2 = ((2 * MFG Cload spec) - CXTAL_EFF - (2 * PCB capacitance))

      C1 = C2 = (36 - 5.5 - (2 * 2.5))

      C1 = C2 = 25.5 pF (always rounded down)

      C1 = C2 = 25 pF (i.e., for hypothetical example crystal external load capacitors)

      User C1 = C2 = 25 pF CLOAD (max.) spec

  4. Maximum start up time user selectable in CKGR_MOR.MOSCXTST[7:0].
  5. Clock Fail Safe Time-out Period is up to 2*8*1/fosc where fosc is the SlowRC oscillator frequency.