13.4.5 Interrupt Control Register 5
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | INTCON5 |
| Offset: | 0x80 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SOFT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| YPWBDED | XPWBDED | WDTE | DMTE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 31 – SOFT Software Generated Soft Trap Status bit
| Value | Description |
|---|---|
1 | Raise software generated soft trap |
0 | Soft trap has not occurred |
Bit 3 – YPWBDED YRAM PWB DED Trap Status bit
| Value | Description |
|---|---|
1 | YRAM PWB DED error event has occurred |
0 | YRAM PWB DED error event has not occurred |
Bit 2 – XPWBDED XRAM PWB DED Trap Status bit
| Value | Description |
|---|---|
1 | XRAM PWB DED error event has occurred |
0 | XRAM PWB DED error event has not occurred |
Bit 1 – WDTE WDT Run Mode Event Status bit
| Value | Description |
|---|---|
1 | WDT event has occurred |
0 | WDT event has not occurred |
Bit 0 – DMTE DMT Event Status bit
| Value | Description |
|---|---|
1 | DMT event has occurred |
0 | DMT event has not occurred |