13.4.3 Interrupt Control Register 3
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | INTCON3 |
| Offset: | 0x78 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPUBET | DMABET | YRAMBET | XRAMBET | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CPUBET CPU Instruction Bus Error Trap Status bit
| Value | Description |
|---|---|
1 | CPU Instruction-bus error has occurred |
0 | CPU Instruction-bus error has not occurred |
Bit 2 – DMABET DMA Bus Error Trap Status bit
| Value | Description |
|---|---|
1 | DMA bus error has occurred |
0 | DMA bus error has not occurred |
Bit 1 – YRAMBET CPU Y Data Bus Error Trap Status bit
| Value | Description |
|---|---|
1 | CPU Y Data bus error has occurred |
0 | CPU Y Data bus error has not occurred |
Bit 0 – XRAMBET CPU X Data Bus Error Trap Status bit
| Value | Description |
|---|---|
1 | CPU X Data bus error has occurred |
0 | CPU X Data bus error has not occurred |