13.4.30 Interrupt Priority Register 3
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | IPC3 |
| Offset: | 0xE4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WDTIP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| C4RDYIP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| C4MONIP[2:0] | C4WARMIP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 0 | |||
Bits 18:16 – WDTIP[2:0] Sleep/Idle Mode WDT Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 10:8 – C4RDYIP[2:0] Clock 4 Ready Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 6:4 – C4MONIP[2:0] Clock 4 Monitor Error Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |
Bits 2:0 – C4WARMIP[2:0] Clock 4 Warming Complete Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |