13.4.6 Interrupt Control and Status Register

Note:

During Debug mode, the ICD can force the interrupts to be disabled. This allows the user code to progress with single stepping even when there are pending interrupts.
The bit fields in the INTTREG register correspond to the value of the vector number, interrupt level and IRQ request flag when an interrupt is presented to the CPU.

Table 13-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	INTTREG
Offset:	0x84


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	IRQCPU		VHOLD
Access	R		R/W
Reset	0		0


Bit	15	14	13	12	11	10	9	8
			ILR[3:0]					VECNUM[8]
Access			R	R	R	R		R
Reset			0	0	0	0		0


Bit	7	6	5	4	3	2	1	0
	VECNUM[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 23 – IRQCPU Interrupt Request from Interrupt Controller to CPU bit^(1,2)

Bit 21 – VHOLD Vector Number Capture Enable bit

Value	Description
`1`	VECNUM[8:0] bits read current value of vector number encoding tree (i.e., highest priority pending interrupt)
`0`	Vector number latched into VECNUM[8:0] at Interrupt Acknowledge and retained until next IACK

Bits 13:10 – ILR[3:0] CPU Interrupt Priority Level bits⁽²⁾

Bits 8:0 – VECNUM[8:0] Vector Number of Pending Interrupt bits⁽²⁾

Vector number of pending interrupt or last acknowledged interrupt. VECNUM = IRQ + 9.

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