13.4.20 Interrupt Enable Register 2
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | IEC2 |
| Offset: | 0xBC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| U2EIE | U2TXIE | U2RXIE | U1EVTIE | U1EIE | U1TXIE | U1RXIE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| I2C2TXIE | I2C2RXIE | I2C2IE | I2C2EIE | I2C1TXIE | I2C1RXIE | I2C1IE | I2C1EIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMP3IE | CMP2IE | CMP1IE | DMA3IE | DMA2IE | DMA1IE | DMA0IE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPI3GIE | SPI3TXIE | SPI3RXIE | SPI2GIE | SPI2TXIE | SPI2RXIE | SPI1GIE | SPI1TXIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – U2EIE UART2 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 30 – U2TXIE UART2 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enabled |
0 | Disabled |
Bit 29 – U2RXIE UART2 Receive Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 28 – U1EVTIE UART1 Event Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 27 – U1EIE UART1 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 26 – U1TXIE UART1 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 | Enabled |
0 | Disabled |
Bit 25 – U1RXIE UART1 Receive Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 23 – I2C2TXIE I2C2 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 22 – I2C2RXIE I2C2 Receive Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 21 – I2C2IE I2C2 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 20 – I2C2EIE I2C2 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 19 – I2C1TXIE I2C2 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 18 – I2C1RXIE I2C2 Receive Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 17 – I2C1IE I2C1 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 16 – I2C1EIE I2C1 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 14 – CMP3IE Comparator 3 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 13 – CMP2IE Comparator 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 12 – CMP1IE Comparator 1 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 11 – DMA3IE Direct Memory Access 3 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 10 – DMA2IE Direct Memory Access 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt is enabled |
0 | Interrupt is not enabled |
Bit 9 – DMA1IE Direct Memory Access 1 Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 8 – DMA0IE Direct Memory Access 1 Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is not enabled |
Bit 7 – SPI3GIE SPI3 General Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt request enabled |
| 0 | Interrupt request not enabled |
Bit 6 – SPI3TXIE SPI3 Transmitter Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt request enabled |
| 0 | Interrupt request not enabled |
Bit 5 – SPI3RXIE SPI3 Receiver Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |
Bit 4 – SPI2GIE SPI2 General Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |
Bit 3 – SPI2TXIE SPI2 Transmitter Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |
Bit 2 – SPI2RXIE SPI2 Receiver Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |
Bit 1 – SPI1GIE SPI1 General Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |
Bit 0 – SPI1TXIE SPI1 Transmitter Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt request enabled |
0 | Interrupt request not enabled |