9.7.44 I3CC SCL Low Master Extended Timeout Register
| Name: | I3CC_SCL_LOW_MST_EXT_TIMEOUT |
| Offset: | 0x23C |
| Reset: | 0x003567E0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SCL_LOW_MST_TIMEOUT_COUNT[25:24] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SCL_LOW_MST_TIMEOUT_COUNT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SCL_LOW_MST_TIMEOUT_COUNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SCL_LOW_MST_TIMEOUT_COUNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 25:0 – SCL_LOW_MST_TIMEOUT_COUNT[25:0] Low Bus Reset Pattern Count
Defines the number of core clock periods to count for generation of the SCL low bus reset pattern.