9.7.20 I3CC Response Queue Port Register
| Name: | I3CC_RESPONSE_QUEUE_PORT |
| Offset: | 0x0C4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ERR_STATUS[3:0] | TID[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA_LENGTH[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA_LENGTH[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:28 – ERR_STATUS[3:0] Response Error Status
Indicates the Response status for the processed command (i.e., either success or the error type encountered).
| Value | Name | Description |
|---|---|---|
| 0 | SUCCESS | Transfer successful, no error |
| 1 | CRC | CRC error |
| 2 | PARITY | Parity error |
| 3 | FRAME | Frame error |
| 4 | ADDR_HEADER | Address header error |
| 5 | NACK | Address NACK’ed or Dynamic Address Assignment NACK’ed |
| 6 | OVL | Receive overflow or transfer underflow error |
| 7 | – | Reserved |
| 8 | ABORTED | Aborted |
| 9–15 | – | Reserved |
Bits 27:24 – TID[3:0] Command/Response Transaction ID
This value must match the value of field TID for a previously enqueued command descriptor that was sent on the bus.
Bits 15:0 – DATA_LENGTH[15:0] Data Length/Device Count
For Write transfer: Remaining data length (in bytes).
For Read transfer: Received data length (in bytes).
For Address Assignment: Remaining device count.