9.7.41 I3CC SCL Termination Bit Low count Timing Register
This register is not part of the HCI standard.
| Name: | I3CC_SCL_EXT_TERMN_LCNT_TIMING |
| Offset: | 0x22C |
| Reset: | 0x00030000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I3C_EXT_TERMN_LCNT[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – I3C_EXT_TERMN_LCNT[3:0] I3C Read Termination Bit Low count.
Extended I3C read termination bit low count for I3C Read transfers. Termination bit low period is derived based on the SDR speed as shown below:
SDR0 speed: I3C_PP_LCNT + I3C_EXT_TERMN_LCNT
SDR1 speed: I3C_EXT_LCNT_1 + I3C_EXT_TERMN_LCNT
SDR2 speed: I3C_EXT_LCNT_2 + I3C_EXT_TERMN_LCNT
SDR3 speed: I3C_EXT_LCNT_3 + I3C_EXT_TERMN_LCNT
SDR4 speed: I3C_EXT_LCNT_4 + I3C_EXT_TERMN_LCNT