9.7.42 I3CC SDA Hold and Mode Switch Delay Timing Register
This register is not part of the HCI standard.
| Name: | I3CC_SDA_HOLD_SWITCH_DLY_TIMING |
| Offset: | 0x230 |
| Reset: | 0x00010000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SDA_TX_HOLD[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 1 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SDA_PP_OD_SWITCH_DLY[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDA_OD_PP_SWITCH_DLY[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 18:16 – SDA_TX_HOLD[2:0] I3CC_SDA Transmit Hold
Controls the hold time (in term of the GCLK period) of the transmit data (SDA) with respect to the I3CC_SCL edge in standard, FM, FM+, SDR and DDR speed mode of operations. Valid values range from 1 to 7.
Bits 10:8 – SDA_PP_OD_SWITCH_DLY[2:0] I3CC_SDA Push-Pull to Open-Drain Switch Delay
Delays the I3CC_SDA pad output with respect to I3CC_SDA pad drive control (in terms of the GCLK period) while switching the transfer from PP1 (Push-Pull mode I3CC_SDA=1) to OD1 (Open-Drain I3CC_SDA=1). Valid values range from 0 to 4.
Bits 2:0 – SDA_OD_PP_SWITCH_DLY[2:0] I3CC_SDA Open-Drain to Push-Pull Switch Delay
Delays the I3CC_SDA pad output with respect to I3CC_SDA pad drive control while switching the transfer from OD1 (Open-Drain mode I3CC_SDA=1) to PP1 (Push-Pull mode I3CC_SDA=1). Valid values range from 0 to 4.