9.7.14 I3CC PIO Section Offset Register
| Name: | I3CC_PIO_SECTION_OFFSET |
| Offset: | 0x03C |
| Reset: | 0x000000C0 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SECTION_OFFSET[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECTION_OFFSET[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – SECTION_OFFSET[15:0] PIO Section Offset
Offset of the PIO mode registers of the register map (starting with I3CC_PIO_INTR_STATUS) relative to the base address of the I3CC.