9.7.5 I3CC Reset Control Register
| Name: | I3CC_RESET_CONTROL |
| Offset: | 0x010 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IBI_QUEUE_RST | RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST | CMD_QUEUE_RST | SOFT_RST | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – IBI_QUEUE_RST IBI Queue Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The IBI queues in the I3CC are flushed. Cleared automatically upon IBI queue reset completion. |
Bit 4 – RX_FIFO_RST Receive Queue Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The Receive queues in the I3CC are flushed. Cleared automatically upon Receive queue reset completion. |
Bit 3 – TX_FIFO_RST Transmit Queue Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The Transmit queues in the I3CC are flushed. Cleared automatically upon Transmit queue reset completion. |
Bit 2 – RESP_QUEUE_RST Response Queue Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The Response queues in the I3CC are flushed. Cleared automatically upon Response queue reset completion. |
Bit 1 – CMD_QUEUE_RST Command Queue Software reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The Command queues in the I3CC are flushed. Cleared automatically upon Command queue reset completion. |
Bit 0 – SOFT_RST Core Software Reset
Cleared automatically upon I3CC reset completion. Resets all queues in the I3CC.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The I3CC is reset and disabled. All registers return to their reset values, and the software must re-initialize the I3CC. |