9.7.48 I3CC Present State Debug Register
| Name: | I3CC_PRESENT_STATE_DEBUG |
| Offset: | 0x24C |
| Reset: | 0x10000003 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HC_IDLE | CMD_TID[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CM_TFR_ST_STATUS[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CM_TFR_STATUS[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDA_LINE_SIGNAL_LEVEL | SCL_LINE_SIGNAL_LEVEL | ||||||||
| Access | R | R | |||||||
| Reset | 1 | 1 |
Bit 28 – HC_IDLE I3CC Idle
| Value | Name | Description |
|---|---|---|
| 0 | HC_NOT_IDLE | I3CC is not in Idle state. |
| 1 | HC_IDLE | I3CC is in Idle state. All of the queues (Command, Response, IBI) and buffers (Transmit and Receive) are empty. |
Bits 27:24 – CMD_TID[3:0] Command Transaction ID
The Transaction ID is an optional software-defined tag for every command. It is useful for detection of the currently executed command while scheduling transfers.
Bits 21:16 – CM_TFR_ST_STATUS[5:0] I3CC Transfer State Status
Indicates the state of transfer that the I3CC is currently executing.
| Value | Name | Description |
|---|---|---|
| 0x00 | IDLE | I3CC is in the Idle state, waiting for commands from the application or for target-initiated IBIs |
| 0x01 | START | START Generation state |
| 0x02 | RESTART | RESTART Generation state |
| 0x03 | STOP | STOP Generation state |
| 0x04 | START_HOLD | START Hold Generation for the target-initiated START state |
| 0x05 | BCAST_WRITE | Broadcast Write Address Header(0x7E,W) Generation state |
| 0x06 | BCAST_READ | Broadcast Read Address Header(0x7E,R) Generation state |
| 0x07 | DAA | Dynamic Address Assignment state |
| 0x08 | ADDR | Target Address Generation state |
| 0x0B | CCC | CCC Byte Generation state |
| 0x0C | HDR | HDR Command Generation state |
| 0x0D | WR | Write Data Transfer state |
| 0x0E | RD | Read Data Transfer state |
| 0x0F | IBI_ADDR_READ | IBI Address Read Data state |
| 0x10 | IBI_DIS | IBI Auto-Disable state |
| 0x11 | HDR_DDR_CRC | HDR-DDR CRC Data Generation/Receive state |
| 0x12 | CLOCK_EXT | Clock Extension state |
| 0x13 | HALT | Halt state |
| 0x14 | IBI_READ | IBI Read Data state |
Bits 13:8 – CM_TFR_STATUS[5:0] I3CC Transfer Type Status
Indicates the type of transfer the I3CC is currently executing.
| Value | Name | Description |
|---|---|---|
| 0x0 | IDLE | I3CC is in the Idle state, waiting for commands from the application, or for target-initiated IBIs |
| 0x1 | BCAST_WRITE | Broadcast CCC Write transfer |
| 0x2 | TARGET_WRITE | Directed CCC Write transfer |
| 0x3 | TARGET_READ | Directed CCC Read transfer |
| 0x4 | ENTDAA | ENTDAA Address Assignment transfer |
| 0x5 | SETDASA | SETDASA Address Assignment transfer |
| 0x6 | I3C_SDR_WRITE | Private I3C SDR Write transfer |
| 0x7 | I3C_SDR_READ | Private I3C SDR Read transfer |
| 0x8 | I2C_SDR_WRITE | Private I2C SDR Write transfer |
| 0x9 | I2C_SDR_READ | Private I2C SDR Read transfer |
| 0xC | HDR_DDR_WRITE | Private HDR Double-Data Rate (DDR) Write transfer |
| 0xD | HDR_DDR_READ | Private HDR Double-Data Rate (DDR) Read transfer |
| 0xE | IBI | Servicing IBI transfer |
| 0xF | HALTED | I3CC is in the Halt state, waiting for the application to resume through I3CC_HC_CONTROL |
Bit 1 – SDA_LINE_SIGNAL_LEVEL SDA Line Signal Level
Used to check the I3CC_SDA line level to recover from errors and for debugging.
Bit 0 – SCL_LINE_SIGNAL_LEVEL I3CC_SCL Line Signal Level
Used to check the I3CC_SCL line level to recover from errors and for debugging.