9.7.23 I3CC Queue Threshold Control Register
| Name: | I3CC_QUEUE_THLD_CTRL |
| Offset: | 0x0D0 |
| Reset: | 0x01000101 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IBI_STATUS_THLD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IBI_DATA_SEGMENT_SIZE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RESP_BUF_THLD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD_EMPTY_BUF_THLD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 31:24 – IBI_STATUS_THLD[7:0] IBI Status Threshold
Controls the generation of I3CC_PIO_INTR_STATUS.IBI_STATUS_THLD_STAT interrupt, based on the value of the IBI queue’s outstanding IBI statuses.
0: Interrupt is triggered when the outstanding IBI status count in the IBI queue reaches 1 or above.
N: Interrupt is triggered when the outstanding IBI status count in the IBI queue reaches N+1 or above.
Each IBI status entry can represent either the complete IBI payload (if the IBI payload byte size <= 4 * IBI_DATA_SEGMENT_SIZE), or a segment of the IBI payload (if the IBI payload byte size > 4 * IBI_DATA_SEGMENT_SIZE).
Bits 23:16 – IBI_DATA_SEGMENT_SIZE[7:0] IBI Data Segment Size
IBI data segment size in 32-bit words.
The minimum supported segment size is 1 (4 bytes) and the maximum supported size is 63.
Enables the slicing of the incoming IBI data to generate individual status and support the cut-through readout of a long IBI payload data.
Bits 15:8 – RESP_BUF_THLD[7:0] Response Ready Buffer Threshold
Controls the minimum number of response queue entries needed to trigger I3CC_PIO_INTR_STATUS.RESP_READY_STAT interrupt.
The valid range is 0 to 7.
0: Interrupt is triggered when response queue contains 1 entry (32-bit word).
N: Interrupt is triggered when response queue contains at least N+1 entries (32-bit word).
Bits 7:0 – CMD_EMPTY_BUF_THLD[7:0] Command Ready Buffer Threshold
Controls the minimum number of empty command queue entries needed to trigger I3CC_PIO_INTR_STATUS.CMD_QUEUE_READY_STAT interrupt.
The valid range is 0 to 15.
0: Interrupt is issued when command queue is completely empty.
N: Interrupt is issued when command queue contains at least N empty entries.