Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
- 9.1 Overview
- 9.2 Ethernet MAC (GMAC)
- 9.3 Flexible Serial Communication Controller (FLEXCOM)
- 9.4 Quad Serial Peripheral Interface (QSPI)
- 9.5 Secure Digital MultiMedia Card Controller (SDMMC)
- 9.6 Controller Area Network (MCAN)
- 9.7 I3C Controller (I3CC)
  - 9.7.1 Description
  - 9.7.2 Embedded Characteristics
  - 9.7.3 Block Diagram
  - 9.7.4 Product Dependencies
  - 9.7.5 Functional Description
  - 9.7 Register Summary
    - 9.7.1 I3CC HCI Version Register
      I3CC HCI Version Register
    - 9.7.2 I3CC Controller Control Register
      I3CC Controller Control Register
    - 9.7.3 I3CC Controller Device Address Register
      I3CC Controller Device Address Register
    - 9.7.4 I3CC Controller Capabilities Register
      I3CC Controller Capabilities Register
    - 9.7.5 I3CC Reset Control Register
      I3CC Reset Control Register
    - 9.7.6 I3CC Present State Register
      I3CC Present State Register
    - 9.7.7 I3CC Interrupt Status Register
      I3CC Interrupt Status Register
    - 9.7.8 I3CC Interrupt Status Enable Register
      I3CC Interrupt Status Enable Register
    - 9.7.9 I3CC Interrupt Signal Enable Register
      I3CC Interrupt Signal Enable Register
    - 9.7.10 I3CC Interrupt Force Register
      I3CC Interrupt Force Register
    - 9.7.11 I3CC Device Address Table Section Offset Register
      I3CC Device Address Table Section Offset Register
    - 9.7.12 I3CC Device Characteristics Table Section Offset Register
      I3CC Device Characteristics Table Section Offset Register
    - 9.7.13 I3CC Ring Headers Section Offset Register
      I3CC Ring Headers Section Offset Register
    - 9.7.14 I3CC PIO Section Offset Register
      I3CC PIO Section Offset Register
    - 9.7.15 I3CC Extended Capabilities Section Offset Register
      I3CC Extended Capabilities Section Offset Register
    - 9.7.16 I3CC IBI Notify Control Register
      I3CC IBI Notify Control Register
    - 9.7.17 I3CC Device Context Base Address Low Register
      I3CC Device Context Base Address Low Register
    - 9.7.18 I3CC Device Context Base Address High Register
      I3CC Device Context Base Address High Register
    - 9.7.19 I3CC Command Queue Port Register
      I3CC Command Queue Port Register
    - 9.7.20 I3CC Response Queue Port Register
      I3CC Response Queue Port Register
    - 9.7.21 I3CC Transfer Data Port Register
      I3CC Transfer Data Port Register
    - 9.7.22 I3CC IBI Port Register
      I3CC IBI Port Register
    - 9.7.23 I3CC Queue Threshold Control Register
      I3CC Queue Threshold Control Register
    - 9.7.24 I3CC Transfer Data Buffer Threshold Control Register
      I3CC Transfer Data Buffer Threshold Control Register
    - 9.7.25 I3CC Queue Size Register
      I3CC Queue Size Register
    - 9.7.26 I3CC PIO Interrupt Status Register
      I3CC PIO Interrupt Status Register
    - 9.7.27 I3CC PIO Interrupt Status Enable Register
      I3CC PIO Interrupt Status Enable Register
    - 9.7.28 I3CC PIO Interrupt Signal Enable Register
      I3CC PIO Interrupt Signal Enable Register
    - 9.7.29 I3CC PIO Interrupt Force Register
      I3CC PIO Interrupt Force Register
    - 9.7.30 I3CC Hardware Identification Header Register
      I3CC Hardware Identification Header Register
    - 9.7.31 I3CC Component Manufacturer Register
      I3CC Component Manufacturer Register
    - 9.7.32 I3CC Component Version Register
      I3CC Component Version Register
    - 9.7.33 I3CC Component Type Register
      I3CC Component Type Register
    - 9.7.34 I3CC Bus Timing Header Register
      I3CC Bus Timing Header Register
    - 9.7.35 I3CC SCL I3C Open-Drain Timing Register
      I3CC SCL I3C Open-Drain Timing Register
    - 9.7.36 I3CC SCL I3C Push-Pull Timing Register
      I3CC SCL I3C Push-Pull Timing Register
    - 9.7.37 I3CC SCL I2C Fast Mode Timing Register
      I3CC SCL I2C Fast Mode Timing Register
    - 9.7.38 I3CC SCL I2C Fast Mode Plus Timing Register
      I3CC SCL I2C Fast Mode Plus Timing Register
    - 9.7.39 I3CC SCL I2C Standard Speed Timing Register
      I3CC SCL I2C Standard Speed Timing Register
    - 9.7.40 I3CC SCL Extended Low Count Timing Register
      I3CC SCL Extended Low Count Timing Register
    - 9.7.41 I3CC SCL Termination Bit Low count Timing Register
      I3CC SCL Termination Bit Low count Timing Register
    - 9.7.42 I3CC SDA Hold and Mode Switch Delay Timing Register
      I3CC SDA Hold and Mode Switch Delay Timing Register
    - 9.7.43 I3CC Bus Free Timing Register
      I3CC Bus Free Timing Register
    - 9.7.44 I3CC SCL Low Master Extended Timeout Register
      I3CC SCL Low Master Extended Timeout Register
    - 9.7.45 I3CC Debug Specific Header Register
      I3CC Debug Specific Header Register
    - 9.7.46 I3CC Queue Status Level Register
      I3CC Queue Status Level Register
    - 9.7.47 I3CC Data Buffer Status Level Register
      I3CC Data Buffer Status Level Register
    - 9.7.48 I3CC Present State Debug Register
      I3CC Present State Debug Register
    - 9.7.49 I3CC Controller Extended Header Register
      I3CC Controller Extended Header Register
    - 9.7.50 I3CC Controller Configuration Register
      I3CC Controller Configuration Register
- 9.8 Pulse Width Modulation Controller (PWM)
- 9.9 Timer Counter (TC)
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information

9.7.2 I3CC Controller Control Register

Name:	I3CC_HC_CONTROL
Offset:	0x004
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	BUS_ENABLE	RESUME	ABORT
Access	R/W	R/W	R/W
Reset	0	0	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
								HOT_JOIN_CTRL
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
	I2C_DEV_PRESENT							IBA_INCLUDE
Access	R/W							R/W
Reset	0							0

Bit 31 – BUS_ENABLE I3CC Bus Enable

Value	Description
0	Disables I3CC bus operations when writing a ‘0’ or indicates the I3CC operations are completed when reading ‘0’.
1	Enables I3CC bus operations.

Bit 30 – RESUME I3CC Resume

Used to resume I3CC operation following the Halt state. The I3CC enters the Halt state (as indicated in I3CC_PRESENT_STATE) as a result of any type of error occurring in a transfer. The error type is indicated in I3CC_RESPONSE_QUEUE_PORT.ERR_STATUS. After the I3CC has entered the Halt state, the application must write the value ‘1’ to the RESUME bit to resume I3CC operation. The I3CC automatically clears the RESUME bit once it has resumed making transfers, that is, has initiated the next command.

Value	Name	Description
0	RUNNING	The I3CC running.
1	SUSPENDED	The I3CC is suspended.

Bit 29 – ABORT I3CC Abort

Value	Description
0	The driver clears the ABORT bit to allow operation on the bus.
1	The I3CC aborts a transfer by issuing the STOP condition on the I3C Bus after the complete data byte is transferred or received.

Bit 8 – HOT_JOIN_CTRL Hot-Join ACK/NACK Control

Value	Description
0	ACK Hot-Join request.
1	NACK and send broadcast CCC to disable Hot-Join.

Bit 7 – I2C_DEV_PRESENT I2C Device Present on Bus

Value	Description
0	Legacy I2C devices must not be present on the I3C bus.
1	Legacy I2C devices can be present on the I3C bus.

Bit 0 – IBA_INCLUDE Include I3C Broadcast Address

Controls whether the I3C broadcast address (0x7E) is included for private transfers. If the I3C broadcast address is not included for private transfers, then In-band Interrupts (IBI) driven from target devices might not win the arbitration, potentially delaying acceptance of the IBIs.

Value	Description
0	Do not include I3C Broadcast Address for private transfers.
1	Include I3C Broadcast Address for private transfers.

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