9.7.26 I3CC PIO Interrupt Status Register
| Name: | I3CC_PIO_INTR_STATUS |
| Offset: | 0x0E0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRANSFER_ERR_STAT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRANSFER_ABORT_STAT | RESP_READY_STAT | CMD_QUEUE_READY_STAT | IBI_STATUS_THLD_STAT | RX_THLD_STAT | TX_THLD_STAT | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – TRANSFER_ERR_STAT Transfer Error Status
The I3CC sets this bit to ‘1’ when any transfer error occurs on the I3C bus. The error type for this error is available in the response structure corresponding to this transfer/command.
Writing '0' clears this bit.
Bit 5 – TRANSFER_ABORT_STAT Transfer Abort Status
The I3CC sets this bit to ‘1’ when any transfer is aborted.
Writing '0' clears this bit.
Bit 4 – RESP_READY_STAT Response Ready Status
The I3CC sets this bit to ‘1’ when the number of response queue entries meets or exceeds the value of QUEUE_THLD_CTRL.RESP_BUF_THLD.
The I3CC automatically clears this field to ‘0’ when the number of Response Queue entries falls below the RESP_BUF_THLD threshold.
Bit 3 – CMD_QUEUE_READY_STAT Command Queue Ready Status
The I3CC sets this bit to ‘1’ when the number of empty command queue entries meets or exceeds the value of QUEUE_THLD_CTRL.CMD_EMPTY_BUF_THLD.
The I3CC automatically clears this field to ‘0’ when the number of empty command queue entries falls below the CMD_EMPTY_BUF_THLD threshold.
Bit 2 – IBI_STATUS_THLD_STAT IBI Status Threshold Status
The I3CC sets this bit to ‘1’ when the number of IBI status entries in the IBI queue reaches the QUEUE_THLD_CTRL.IBI_STATUS_THLD threshold.
The I3CC automatically clears this field to ‘0’ when the number of IBI status entries in the IBI queue falls below the IBI_STATUS_THLD threshold as a result of application reads.
Bit 1 – RX_THLD_STAT Receive Data Buffer Threshold Status
The I3CC sets this bit to ‘1’ when the number of entries in the receive data queue meets or exceeds the value of DATA_BUFFER_THLD_CTRL.RX_BUF_THLD.
The I3CC automatically clears this field to ‘0’ when the number of receive data queue entries falls below the RX_BUF_THLD threshold.
Bit 0 – TX_THLD_STAT Transmit Data Buffer Threshold Status
The I3CC sets this bit to ‘1’ when the number of available entries in the transmit data queue meets or exceeds the value of DATA_BUFFER_THLD_CTRL.TX_BUF_THLD.
The I3CC automatically clears this field to ‘0’ when the number of transmit data queue entries falls below the TX_BUF_THLD threshold.