9.7.7 I3CC Interrupt Status Register
| Name: | I3CC_INTR_STATUS |
| Offset: | 0x020 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HC_INTERNAL_ERR_STAT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 10 – HC_INTERNAL_ERR_STAT I3CC Internal Error
Reflects the interrupt status that is populated upon non-recoverable internal error of the I3CC.
Cleared either by the software writing it to ‘1’ or based on queue operations.