9.7.43 I3CC Bus Free Timing Register
This register is not part of the HCI standard.
| Name: | I3CC_BUS_FREE_TIMING |
| Offset: | 0x234 |
| Reset: | 0x00000020 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| I3C_HC_FREE[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I3C_HC_FREE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – I3C_HC_FREE[15:0] I3C I3CC Free Count
In Pure Bus systems, this field represents tCAS. In Mixed Bus systems, this field is expected to be programmed to tLOW of I2C timing.