9.7.40 I3CC SCL Extended Low Count Timing Register
This register is not part of the HCI standard.
| Name: | I3CC_SCL_EXT_LCNT_TIMING |
| Offset: | 0x228 |
| Reset: | 0x20202020 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| I3C_EXT_LCNT_4[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| I3C_EXT_LCNT_3[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| I3C_EXT_LCNT_2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I3C_EXT_LCNT_1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – I3C_EXT_LCNT_4[7:0] I3C Extended Low Count Register 4
SDR4 uses this register field for data transfer.
Bits 23:16 – I3C_EXT_LCNT_3[7:0] I3C Extended Low Count Register 3
SDR3 uses this register field for data transfer.
Bits 15:8 – I3C_EXT_LCNT_2[7:0] I3C Extended Low Count Register 2
SDR2 uses this register field for data transfer.
Bits 7:0 – I3C_EXT_LCNT_1[7:0] I3C Extended Low Count Register 1
SDR1 uses this register field for data transfer.