9.7.34 I3CC Bus Timing Header Register
| Name: | I3CC_BUS_TIMING_HEADER |
| Offset: | 0x210 |
| Reset: | 0x00000CC0 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CAP_LEN[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CAP_LEN[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CAP_ID[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:8 – CAP_LEN[15:0] Capability Structure Length
Number of bus timing registers of this Capability Structure including this one.
Reads as 0x000C.
Bits 7:0 – CAP_ID[7:0] Extended Capability ID
Indicates this Extended Capability Structure is a bus timing structure.
Reads as 0xC0.