9.7.35 I3CC SCL I3C Open-Drain Timing Register
This register is not part of the HCI standard.
| Name: | I3CC_SCL_I3C_OD_TIMING |
| Offset: | 0x214 |
| Reset: | 0x000A0010 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| I3C_OD_HCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I3C_OD_LCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
Bits 23:16 – I3C_OD_HCNT[7:0] I3C Open-Drain High Count
SCL open-drain high count (I3C) for I3C transfers targeted to I3C devices.
Bits 7:0 – I3C_OD_LCNT[7:0] I3C Open-Drain Low Count
SCL open-drain low count for I3C transfers targeted to I3C devices.