9.7.24 I3CC Transfer Data Buffer Threshold Control Register


Bit	31	30	29	28	27	26	25	24
						RX_START_THLD[2:0]
Access						R/W	R/W	R/W
Reset						0	0	1


Bit	23	22	21	20	19	18	17	16
						TX_START_THLD[2:0]
Access						R/W	R/W	R/W
Reset						0	0	1


Bit	15	14	13	12	11	10	9	8
						RX_BUF_THLD[2:0]
Access						R/W	R/W	R/W
Reset						0	0	1


Bit	7	6	5	4	3	2	1	0
						TX_BUF_THLD[2:0]
Access						R/W	R/W	R/W
Reset						0	0	1

Bits 26:24 – RX_START_THLD[2:0] Receive Start Threshold

When preparing to initiate a Read transfer on the I3C bus, the I3CC waits until the receive buffer has at least the programmed number of 32-bit word entries available to receive the data bytes.

The following configurable options are provided.

Store and Forward mode:

If the threshold number of entries is set to the receive buffer size (i.e. 64), then the I3CC waits for one of the following to be true to initiate the read command:

Entire receive buffer to be empty, if the data length is more than the receive buffer size
The data length number of locations to be empty in the receive buffer, if data length is smaller than the receive buffer size

Threshold mode:

In this case, if the threshold number of entries is less than the receive buffer size (i.e. 64), then the I3CC initiates the read command as soon as the programmed number of entries are empty in the receive buffer.

Value	Name	Description
0	1_ENTRY	1 available FIFO entry
1	4_ENTRIES	4 available FIFO entries
2	8_ENTRIES	8 available FIFO entries
3	16_ENTRIES	16 available FIFO entries
4	32_ENTRIES	32 available FIFO entries
5	64_ENTRIES	64 available FIFO entries

Bits 18:16 – TX_START_THLD[2:0] Transmit (Transfer) Start Threshold

When preparing to initiate a Write transfer on the I3C bus, the I3CC waits until the software has written at least the programmed number of 32-bit word entries into the transmit buffer.

The following configurable options are provided.

Store and Forward mode:

If the threshold number of entries is set to the transmit buffer size (i.e. 64), then the I3CC waits for one of the following to be true to initiate the write command:

Entire transmit buffer to be full, if the data length is more than the transmit buffer size.
The data length number of locations to be filled in the transmit buffer, if data length is smaller than the transmit buffer size.

Threshold mode:

In this case, if the threshold number of entries is less than the transmit buffer size (i.e. 64), then the I3CC initiates the write command as soon as the programmed number of entries are filled in the transmit buffer.

Value	Name	Description
0	1_WORD	1 available transmit data
1	4_WORDS	4 available transmit data
2	8_WORDS	8 available transmit data
3	16_WORDS	16 available transmit data
4	32_WORDS	32 available transmit data
5	64_WORDS	64 available transmit data

Bits 10:8 – RX_BUF_THLD[2:0] Receive Buffer Threshold

Encodes the minimum number of receive FIFO entries of data received, in 32-bit words, that triggers the I3CC_PIO_INTR_STATUS.RX_THLD_STAT interrupt.

If the programmed value encodes for more than 64 data words, then the threshold is set to 64 entries.

Value	Name	Description
0	1_WORD	1 received data
1	4_WORDS	4 received data
2	8_WORDS	8 received data
3	16_WORDS	16 received data
4	32_WORDS	32 received data
5	64_WORDS	64 received data

Bits 2:0 – TX_BUF_THLD[2:0] Transmit Buffer Threshold

Encodes the minimum number of available transmit FIFO entries, in 32-bit words, that triggers the I3CC_PIO_INTR_STATUS.TX_THLD_STAT interrupt.

If the programmed value encodes for more than 64 entries, then the threshold is set to 64 entries.

Value	Name	Description
0	1_ENTRY	1 available FIFO entry
1	4_ENTRIES	4 available FIFO entries
2	8_ENTRIES	8 available FIFO entries
3	16_ENTRIES	16 available FIFO entries
4	32_ENTRIES	32 available FIFO entries
5	64_ENTRIES	64 available FIFO entries

Name:	I3CC_DATA_BUFFER_THLD_CTRL
Offset:	0x0D4
Reset:	0x01010101
Property:	Read/Write