9.3.9.9 ULPI_RAW_DATA_REG (Synchronous mode) Bit Definitions
When the PHY’s Synchronous mode is used, this register stores the last RxCmd.
Because RxCmds are received in the PHY clock domain and this register is read in the CPU clock domain, RxCmds may be missed if they are concurrent and the CPU clock is slower than the PHY clock. This should not be an issue for CarKit negotiation because this process lasts for over 1 ms, but this feature should not be relied upon to monitor transactions carried out at USB bus speed.
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| 7 | alt_int | 0 | Asserted when a non-USB interrupt occurs. In particular, it must be set if an unmasked event occurs on any bit of the PHY’s CarKit Interrupt Latch register. |
| 6 | ID | 0 | Set to the value of the IDDIG (valid 50 ms after IDPULLUP is asserted). |
| [5:4] | RxEvent[1:0] | 0 | Encoded UTMI event signals are given in Table 9-73. |
| [3:2] | VbusState[1:0] | 0 | Encoded Vbus voltage state. 00: Vbus < VB_Sess_END 01: VB_Sess_END < = Vbus < VB_Sess_VLD . . 10: VB_Sess_VLD < = Vbus < VB_Vbus_VLD 11: VB_Sess_VLD < = Vbus |
| [1:0] | LineState[1:0] | 0 | UTMI+ LineState signals |