49.4 Power Supply DC Module Electrical Specifications
| DC Characteristics | Standard Operating Conditions: VDD33
= VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +85°C for Industrial Temperature -40°C ≤ TA ≤ +125°C for Extended Temperature | ||||||
|---|---|---|---|---|---|---|---|
| Parameter Number | Symbol | Characteristics | Min. | Typ | Max. | Units | Conditions |
| REG_37 | VDD33/VDDIO(1) | VDD/VDDIO Input Voltage Range | 1.9 | 3.3 | 3.6 | V | — |
| REG_39 | AVDD(1) | AVDD Input Voltage Range | >= 1.9 VDD33-0.3 | — | VDD33+0.3 <= 3.6 | V | — |
| REG_41 | VUSB3V3 | VUSB3V3 Input Voltage Range | 3 | — | 3.6 | V | — |
| PMU Specification (MLDO Mode) | |||||||
| REG_43 | MLDO_VOUT(2) | Output Voltage Range | — | 1.35 | — | V | — |
| REG_45 | MLDO_VIN(2) | Input Voltage Range (Same as VDD/VDDIO) | 1.9 | 3.3 | 3.6 | V | — |
| PMU Specification (Buck Mode) | |||||||
| REG_67 | BUCK_VOUT(2) | Output Voltage Range | — | 1.35 | — | V | — |
| REG_69 | BUCK_VIN(2) | Input Voltage Range (Same as VDD/VDDIO) | 2.4 | 3.3 | 3.6 | V | — |
| CLDO Specification | |||||||
| REG_93 | CLDO_VIN | Input Voltage Range (Output from PMU) | 1.3 | 1.35 | 1.4 | V | — |
| REG_94 | CLDO_VOUT | Output Voltage Range | — | 1.2 | — | V | — |
| POR, BOR, RESET Specification | |||||||
| REG_105 | SVDD_R | VDD Rise Ramp Rate to Ensure Internal Power-on Reset Signal | — | 0.0055 | 0.011 | V/µs | 600 µs (typical) – 30 µs (minimum) at 3.3V |
| REG_107 | SVDD_F | VDD Falling Ramp Rate to Ensure Internal Power-on Reset Signal | — | 0.0055 | 0.011 | V/µs | 600 µs (typical) – 30 µs (minimum) at 3.3V |
| REG_109 | VPOR+ | Power-on Reset (voltage threshold level on VDD rising) | 1.53 | 1.55 | 1.61 | V | VDD33/VDDIO voltage must remain at VSS for a minimum of 200 µs to ensure POR. VDDIO Power-up/Power-down (see parameter REG_105, VDDIO Ramp Rate) |
| REG_111 | VPOR- | Power-on Reset (voltage threshold level on VDD falling) | 1.52 | 1.55 | 1.59 | V | VDD33/VDDIO voltage must remain at VSS for a minimum of 200 µs to ensure POR. VDDIO Power-up/Power-down (see parameter REG_107, VDDIO Ramp Rate) |
| REG_113 | VBOR33 | BOR33 Voltage on VDD transition high to low | — | 1.802 | — | V | — |
| REG_115 | VBOR33LH | BOR33 Voltage on VDD transition low to high | — | 1.834 | — | V | — |
| REG_119 | VBOR33HYS | Brown-out Hysteresis | 25 | 32 | 46 | mV | — |
| REG_121 | VBOR12 | BOR12 (1.2V) Voltage transition high to low | — | 1.1 | — | V | — |
| REG_123 | VBOR12LH | BOR12 Voltage transition low to high | — | 1.1 | — | V | — |
| REG_125 | VBOR12HYS | Brown-out Hysteresis | 2 | 4 | 10 | mV | — |
| REG_127 | VZPBOR33 | Zero Power BOR (high to low) | — | 1.787 | — | V | — |
| REG_128 | VZPBOR33LH | Zero Power BOR (low to high) | — | 1.85 | — | V | — |
| REG_129 | TPU | Power-up Period (internal regulator enabled) | — | 0.650 | 1.2 | ms | Time till PMU, CLDO output are available |
| REG_135 | TSYSDLY | System Delay Period (without security) | — | 4 | — | ms | Before CPU start executing instruction from Flash. Includes Reload Device Configuration Fuses, Boot ROM execution time with authentication disable |
| REG_139 | TRST | External RESET valid active pulse width (low) | 3 | — | — | µs | Minimum reset active time to guarantee MCU reset for the SoC on MCLR pin. No filter circuit |
| 13 | — | — | µs | Minimum reset active time to guarantee MCU reset for the PIC32WM-BZ6 module on MCLR pin. Reset filter circuit inside the module | |||
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Note:
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