49.19 ADC Electrical Specifications

Table 49-22. ADC AC Electrical Specifications
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
Device Supply
ADC_1	AVDD	ADC Core Supply	AVDD(minimum)	—	AVDD(maximum)	V	—
Reference Inputs
ADC_3	VREF	ADC Reference Voltage	—	—	AVDD	V	Internal Reference
Analog Input Range
ADC_7	AFS	Full-Scale Analog Input Signal Range	AVSS	—	VREF	V	Single-Ended Mode

Table 49-23. Single-Ended Mode ADC AC Electrical Specifications (Dedicated Core - ADC0)
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
Single-Ended Mode ADC Accuracy
SADC_11	Res	Resolution	6	—	12	bits	Selectable 6, 8, 10, 12-bit Resolution Ranges
SADC_13	ENOB^{(1, 2)}	Effective Number of bits	10	10.4	10.8	bits	1 MSPS, 12-bit Resolution mode VREF = AVDD = VDDIO = 3.3V
SADC_19	INL	Integral Nonlinearity	—	-1.6/+1.3	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_25	DNL	Differential Nonlinearity	—	-1.0/+1.9	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_31	GERR	Gain Error	—	-0.8	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_37	EOFF	Offset Error	—	0.1	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
Single-Ended Mode ADC Dynamic Performance
SADC_49	SINAD	Signal to Noise and Distortion	62	64	—	dB	VREF = AVDD = VDDIO = 3.3V at 12-bit maximum sampling rate
SADC_51	SNR	Signal to Noise ratio	62	—	—
SADC_53	SFDR	Spurious Free Dynamic Range	65	68	—
SADC_55	THD⁽³⁾	Total Harmonic Distortion	—	-83	-78
Note: Characterized with an $Analog Input Sine Wave = \frac{{F T P}_{(\max i m u m)}}{100}$ . For example, ${F T P}_{(\max i m u m)} = \frac{1 M S P S}{100} = 10 k H z \sin e w a v e$ . Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution. Values taken over 7 harmonics. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated.

Table 49-24. Single-Ended Mode ADC AC Electrical Specifications (Shared Core - ADC-SHR)
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
Single-Ended Mode ADC Accuracy
SADC_11	Res	Resolution	6	—	12	bits	Selectable 6, 8, 10 and 12-bit Resolution Ranges
SADC_13	ENOB^{(1, 2)}	Effective Number of bits	10.9	11.1	—	bits	1 MSPS, 12-bit Resolution mode VREF = AVDD = VDDIO = 3.3V
SADC_19	INL	Integral Nonlinearity	—	-1.2/+0.9	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_25	DNL	Differential Nonlinearity	—	-1.0/+1.2	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_31	GERR	Gain Error	—	-1.2	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
SADC_37	EOFF	Offset Error	—	2.6	—	LSB	1 MSPS, VREF = AVDD = VDDIO = 3.3V
Single-Ended Mode ADC Dynamic Performance
SADC_49	SINAD	Signal to Noise and Distortion	67	69	—	dB	VREF = AVDD = VDDIO = 3.3V at 12-bit maximum sampling rate
SADC_51	SNR	Signal to Noise ratio	67	—	—
SADC_53	SFDR	Spurious Free Dynamic Range	78	82	—
SADC_55	THD⁽³⁾	Total Harmonic Distortion	—	-85	-78
Note: Characterized with an $Analog Input Sine Wave = \frac{{F T P}_{(\max i m u m)}}{100}$ . For example, ${F T P}_{(\max i m u m)} = \frac{1 M S P S}{100} = 10 k H z \sin e w a v e$ . Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution. Values taken over 7 harmonics. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated.

Table 49-25. ADC Conversion and Sample AC Electrical Requirements
AC Characteristics			Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics	Min.	Typ	Max.	Units	Conditions
ADC Clock Requirements
ADC_57	TQ	ADC Controller Clock Period	1/fADC_TQ	—	—	ns	—
ADC_57a	TAD	ADC Core Clock Period	1/fADC_TAD	—	1/fADC_TAD	ns	—
ADC_58	fADC_TQ	ADC Controller Clock freq	—	—	FCLK_51	MHz	—
ADC_58a	fADC_TAD	ADC Core Clock Frequency	0.14	—	32	MHz	—
ADC Single-Ended Throughput Rates
ADC_59	F_TP ⁽¹⁾ (Single-Ended Mode)	ADC0-Throughput Rate (Sampling rate) (Single-Ended)	—	—	1	MSPS	12-bit resolution, Rsource Impedance ≤ 50Ω, SAMC = 1
ADC_59	F_TP ⁽¹⁾ (Single-Ended Mode)	ADC-SHR -Throughput Rate (Sampling rate) (Single-Ended)	—	—	1	MSPS	12-bit resolution, Rsource Impedance ≤ 50Ω, SAMC = 1
ADC Conversion and Sample time
ADC_63	T_SAMP	ADC Sample Time (ADC0)	3.5	—	—	TAD	12-bit TAD(minimum), External Analog Input Rsource ≤ 200 Ω, Max ADC Clock, SAMC = 1
		ADC Sample Time (ADC-SHR)	3.5	—	—		12-bit TAD(min), External Analog Input Rsource ≤ 200 Ω, Max ADC Clock
		ADC Sample Time (ADC-SHR with ADCCON1.CVDEN bit = `1`)	10.5	—	—		12-bit TAD(minimum), Ext Analog Input Rsource ≤ 200 Ω, ADCCON2.CVDCPL[2:0] = 111
ADC_65	T_CNV	Conversion Time (Single-Ended Mode)	12.5			TAD	12-bit resolution
			10.5				10-bit resolution
			8.5				8-bit resolution
			6.5				6-bit resolution
Note: ADC Throughput Rate FTP = ((1/((TSAMP + TCNV) × TAD))/(# of user active analog inputs in use on specific target ADC core)). Specification values assume only one AINx channel in use.