49.18 DAC Module Electrical Specifications
| AC Characteristics | Standard Operating Conditions: VDD33 =
VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature | ||||||
|---|---|---|---|---|---|---|---|
| Parameter Number | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
| DAC_1 | DRES | DAC Resolution | — | — | 7 | Bits | — |
| DAC_3 | DCLK | Internal DAC Clock Frequency | — | — | FCLK_53 | MHz | AVDD(minimum) |
| DAC_5 | DSAMP | DAC Sampling Rate | — | — | 0.1 | MSPS | — |
| DAC_7 | VOUT | Output Voltage Linear Range | AVSS+0.05 | — | AVDD-0.05 | V | VREF = AVDD |
| DAC_9 | VREF | DAC Reference Input Option | — | — | AVDD | V | — |
| DAC_11 | CLOAD | DAC Out max load to meet VOUT and TSET | — | — | 40 | pf | — |
| DAC_13 | RLOAD | DAC Out max load to meet VOUT and TSET | 33 | — | — | KΩ | — |
| DAC_15 | Tset | DAC Settling Time (10 LSB step) | — | 1 | 4 | µs | ±2 LSB of final value for step size ≤ 10 Lsb at CLOAD and RLOAD w/ AVDD = 3.3V |
| DAC_17 | Tset_FS | DAC Full Scale Settling Time | — | 1 | 4 | µs | ±2 LSB of final value for step size from 10% to 90% at CLOAD and RLOAD w/ AVDD = 3.3V |
| Single Ended Mode | |||||||
| SDAC_19 | INL | Integral Non Linearity | — | -0.24/+0.19 | — | LSB | VREF = AVDD w/ CLOAD and RLOAD |
| SDAC_21 | DNL | Differential Non Linearity | — | -0.16/+0.12 | — | LSB | |
| SDAC_23 | GERR | Gain Error | — | -0.29 | — | LSB | |
| SDAC_25 | EOFF | Offset Error | — | -0.08 | — | LSB | |