14.3.37 Dedicated ADC Core x Control Register Low (x = 0 to 3)

Name:	ADCORExL
Offset:	0xBD4, 0xBD8, 0xBDC, 0xBE0


Bit	15	14	13	12	11	10	9	8
							SAMC[9:8]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	SAMC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 9:0 – SAMC[9:0] Dedicated ADC Core x Conversion Delay Selection bits

These bits determine the time between the trigger event and the start of conversion in the number of the Core Clock Periods (T_ADCORE). During this time, the ADC Core x still continues sampling. This feature is enabled by the SAMCxEN bits in the ADCON4L register.

Value	Description
`1111111111`	1025 T_ADCORE
. . .
`0000000001`	3 T_ADCORE
`0000000000`	2 T_ADCORE