14.3.7 ADC Control Register 4 Low
Legend: r = Reserved bit
| Name: | ADCON4L |
| Offset: | 0xB0C |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Reserved[3:0] | |||||||||
| Access | r | r | r | r | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMC3EN | SAMC2EN | SAMC1EN | SAMC0EN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 11:8 – Reserved[3:0]
Must be written as ‘0’
Bit 3 – SAMC3EN Dedicated ADC Core 3 Conversion Delay Enable bit
| Value | Description |
|---|---|
1 |
After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC[9:0] bits in the ADCORE2L register |
0 |
After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle |
Bit 2 – SAMC2EN Dedicated ADC Core 2 Conversion Delay Enable bit
| Value | Description |
|---|---|
1 |
After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC[9:0] bits in the ADCORE2L register |
0 |
After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle |
Bit 1 – SAMC1EN Dedicated ADC Core 1 Conversion Delay Enable bit
| Value | Description |
|---|---|
1 |
After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC[9:0] bits in the ADCORE1L register |
0 |
After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle |
Bit 0 – SAMC0EN Dedicated ADC Core 0 Conversion Delay Enable bit
| Value | Description |
|---|---|
1 |
After trigger, the conversion will be delayed and the ADC core will continue sampling during the time specified by the SAMC[9:0] bits in the ADCORE0L register |
0 |
After trigger, the sampling will be stopped immediately and the conversion will be started on the next core clock cycle |