14.3.22 ADC Digital Filter x Control Register (x = 0, 1, 2, 3)
Legend: HSC = Hardware Settable/Clearable bit
| Name: | ADFLxCON |
| Offset: | 0xB6A, 0xB6E, 0xB72, 0xB76 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLEN | MODE[1:0] | OVRSAM[2:0] | IE | RDY | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | HSC/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLCHSEL[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – FLEN Filter Enable bit
| Value | Description |
|---|---|
1 |
Filter is enabled |
0 |
Filter is disabled and the RDY bit is cleared |
Bits 14:13 – MODE[1:0] Filter Mode bits
| Value | Description |
|---|---|
11 |
Averaging mode |
10 |
Reserved |
01 |
Reserved |
00 |
Oversampling mode |
Bits 12:10 – OVRSAM[2:0] Filter Averaging/Oversampling Ratio bits
If MODE[1:0] = 00:
111 = 128x (16-bit result in the ADFLxDAT register is in 12.4
format)
110 = 32x (15-bit result in the ADFLxDAT register is in 12.3
format)
101 = 8x (14-bit result in the ADFLxDAT register is in 12.2
format)
100 = 2x (13-bit result in the ADFLxDAT register is in 12.1
format)
011 = 256x (16-bit result in the ADFLxDAT register is in 12.4
format)
010 = 64x (15-bit result in the ADFLxDAT register is in 12.3
format)
001 = 16x (14-bit result in the ADFLxDAT register is in 12.2
format)
000 = 4x (13-bit result in the ADFLxDAT register is in 12.1
format)
If MODE[1:0] = 11 (12-bit result in the ADFLxDAT register in all
instances):
111 = 256x
110 = 128x
101 = 64x
100 = 32x
011 = 16x
010 = 8x
001 = 4x
000 = 2x
Bit 9 – IE Filter Common ADC Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common ADC interrupt will be generated when the filter result will be ready |
0 |
Common ADC interrupt will not be generated for the filter |
Bit 8 – RDY Oversampling Filter Data Ready Flag bit
This bit is cleared by hardware when the result is read from the ADFLxDAT register.
| Value | Description |
|---|---|
1 |
Data in the ADFLxDAT register are ready |
0 |
The ADFLxDAT register has been read and new data in the ADFLxDAT register are not ready |
Bits 4:0 – FLCHSEL[4:0] Oversampling Filter Input Channel Selection bits
| Value | Description |
|---|---|
| 11111-11100 | Reserved |
| 11011 | AN27 |
| 11010 | AN26 |
| 11001 | Band Gap, 1.2V (AN25) |
| 11000 | Temperature Sensor (AN24) |
| 10111 | AN23 |
| . . . | |
| 00010 |
AN2 |
| 00001 | AN1 |
| 00000 |
AN0 |