14.3.43 ADC Control Register 5 Low
Legend: HSC = Hardware Settable/Clearable bit
| Name: | ADCON5L |
| Offset: | 0xC00 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SHRRDY | C3RDY | C2RDY | C1RDY | C0RDY | |||||
| Access | R/HSC | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHRPWR | C3PWR | C2PWR | C1PWR | C0PWR | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 15 – SHRRDY Shared ADC Core Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC core is powered and ready for operation |
0 |
ADC core is not ready for operation |
Bit 11 – C3RDY Dedicated ADC Core 3 Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC Core 3 is powered and ready for operation |
0 |
ADC Core 3 is not ready for operation |
Bit 10 – C2RDY Dedicated ADC Core 2 Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC Core 2 is powered and ready for operation |
0 |
ADC Core 2 is not ready for operation |
Bit 9 – C1RDY Dedicated ADC Core 1 Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC Core 1 is powered and ready for operation |
0 |
ADC Core 1 is not ready for operation |
Bit 8 – C0RDY Dedicated ADC Core 0 Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC Core 0 is powered and ready for operation |
0 |
ADC Core 0 is not ready for operation |
Bit 7 – SHRPWR Shared ADC Core Power Enable bit
| Value | Description |
|---|---|
1 |
ADC core is powered |
0 |
ADC core is off |
Bit 3 – C3PWR Dedicated ADC Core 3 Power Enable bit
| Value | Description |
|---|---|
1 |
ADC Core 3 is powered |
0 |
ADC Core 3 off |
Bit 2 – C2PWR Dedicated ADC Core 2 Power Enable bit
| Value | Description |
|---|---|
1 |
ADC Core 2 is powered |
0 |
ADC Core 2 is off |
Bit 1 – C1PWR Dedicated ADC Core 1 Power Enable bit
| Value | Description |
|---|---|
1 |
ADC Core 1 is powered |
0 |
ADC Core 1 is off |
Bit 0 – C0PWR Dedicated ADC Core 0 Power Enable bit
| Value | Description |
|---|---|
1 |
ADC Core 0 is powered |
0 |
ADC Core 0 is off |