14.3.5 ADC Control Register 3 Low
Legend: HSC = Hardware Settable/Clearable bit
| Name: | ADCON3L |
| Offset: | 0xB08 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| REFSEL[2:0] | SUSPEND | SUSPCIE | SUSPRDY | SHRSAMP | CNVRTCH | ||||
| Access | R/W | R/W | R/W | R/W | R/W | HSC/R | R/W | HSC/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWLCTRG | SWCTRG | CNVCHSEL[5:0] | |||||||
| Access | R/W | HSC/R | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:13 – REFSEL[2:0] ADC Reference Voltage Selection bits
| Value | VREFH | VREFL |
|---|---|---|
001-111 | Unimplemented: Do not use | |
000 | AVDD | AVSS |
Bit 12 – SUSPEND All ADC Core Triggers Disable bit
| Value | Description |
|---|---|
1 | All new trigger events for the ADC core are disabled |
0 | The ADC core can be triggered |
Bit 11 – SUSPCIE Suspend All ADC Cores Common Interrupt Enable bit
| Value | Description |
|---|---|
1 | Common interrupt will be generated when ADC core triggers are suspended (SUSPEND
bit = |
0 | Common interrupt is not generated for suspend ADC cores event |
Bit 10 – SUSPRDY ADC Core Suspended Flag bit
| Value | Description |
|---|---|
1 | The ADC core is suspended (SUSPEND bit = |
0 | The ADC core has previous conversions in progress |
Bit 9 – SHRSAMP Shared ADC Core Sampling Direct Control bit
This bit should be used with the individual channel conversion trigger
controlled by the CNVRTCH bit. It connects an analog input, specified by the
CNVCHSEL[5:0] bits, to the shared ADC core and allows extending the sampling time.
This bit is not controlled by hardware and must be cleared before the conversion
starts (setting CNVRTCH to ‘1’).
| Value | Description |
|---|---|
1 | Shared ADC core samples an analog input specified by the CNVCHSEL[5:0] bits |
0 | Sampling is controlled by the shared ADC core hardware |
Bit 8 – CNVRTCH Software Individual Channel Conversion Trigger bit
| Value | Description |
|---|---|
1 | Single trigger is generated for an analog input specified by the CNVCHSEL[5:0] bits; when the bit is set, it is automatically cleared by hardware on the next instruction cycle |
0 | Next individual channel conversion trigger can be generated |
Bit 7 – SWLCTRG Software Level-Sensitive Common Trigger bit
| Value | Description |
|---|---|
1 | Triggers are continuously generated for all channels with the software; level-sensitive common trigger selected as a source in the ADTRIGnL and ADTRIGxH registers |
0 | No software, level-sensitive common triggers are generated |
Bit 6 – SWCTRG Software Common Trigger bit
| Value | Description |
|---|---|
1 | Single trigger is generated for all channels with the software; common trigger selected as a source in the ADTRIGnL and ADTRIGxH registers; when the bit is set, it is automatically cleared by hardware on the next instruction cycle |
0 | Ready to generate the next software common trigger |
Bits 5:0 – CNVCHSEL[5:0] Channel No. Selection for Software Individual Channel Conv. Trigger bits
These bits define a channel to be converted when the CNVRTCH bit is set.