14.3.38 Dedicated ADC Core x Control Register High (x = 0 to 3)
- For the 6-bit ADC core resolution
(RES[1:0] =
00), the EISEL[2:0] bits settings, from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit ADC core resolution (RES[1:0] =01), the EISEL[2:0] bits settings, ‘110’ and ‘111’, are not valid and should not be used.
| Name: | ADCORExH |
| Offset: | 0xBD6, 0xBDA, 0xBDE, 0xBE2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EISEL[2:0] | RES[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADCS[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 12:10 – EISEL[2:0] ADC Core x Early Interrupt Time Selection bits
| Value | Description |
|---|---|
111 |
Early interrupt is set and interrupt is generated 8 TADCORE clocks prior to when data are ready |
110 |
Early interrupt is set and interrupt is generated 7 TADCORE clocks prior to when data are ready |
101 |
Early interrupt is set and interrupt is generated 6 TADCORE clocks prior to when data are ready |
100 |
Early interrupt is set and interrupt is generated 5 TADCORE clocks prior to when data are ready |
011 |
Early interrupt is set and interrupt is generated 4 TADCORE clocks prior to when data are ready |
010 |
Early interrupt is set and interrupt is generated 3 TADCORE clocks prior to when data are ready |
001 |
Early interrupt is set and interrupt is generated 2 TADCORE clocks prior to when data are ready |
000 |
Early interrupt is set and interrupt is generated 1 TADCORE clock prior to when data are ready |
Bits 9:8 – RES[1:0] ADC Core x Resolution Selection bits
| Value | Description |
|---|---|
11 |
12-bit resolution |
10 |
10-bit resolution |
01 |
8-bit resolution(1) |
00 |
6-bit resolution(1) |
Bits 6:0 – ADCS[6:0] ADC Core x Input Clock Divider bits
These bits determine the number of Source Clock Periods (TCORESRC) for one Core Clock Period (TADCORE).
| Value | Description |
|---|---|
1111111 |
254 Source Clock Periods |
| . . . | |
0000011 |
6 Source Clock Periods |
0000010 |
4 Source Clock Periods |
0000001 |
2 Source Clock Periods |
0000000 |
2 Source Clock Periods |