14.3.4 ADC Control Register 2 High

Legend: HSC = Hardware Settable/Clearable bit

Name:	ADCON2H
Offset:	0xB06


Bit	15	14	13	12	11	10	9	8
	REFRDY	REFERR					SHRSAMC[9:8]
Access	HSC/R	HSC/R					R/W	R/W
Reset	0	0					0	0


Bit	7	6	5	4	3	2	1	0
	SHRSAMC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – REFRDY Band Gap and Reference Voltage Ready Flag bit

Value	Description
`1`	Band gap is ready
`0`	Band gap is not ready

Bit 14 – REFERR Band Gap or Reference Voltage Error Flag bit

Value	Description
`1`	Band gap was removed after the ADC module was enabled (ADON = `1`)
`0`	No band gap error was detected

Bits 9:0 – SHRSAMC[9:0] Shared ADC Core Sample Time Selection bits

These bits specify the number of shared ADC Core Clock Periods (T_ADCORE) for the shared ADC core sample time (Sample Time = (SHRSAMC[9:0] + 2) * T_ADCORE).

Value	Description
`1111111111`	1025 T_ADCORE
`. . .`
`0000000001`	3 T_ADCORE
`0000000000`	2 T_ADCORE