14.3.35 ADC Level-Sensitive Trigger Control Register Low
| Name: | ADLVLTRGL |
| Offset: | 0xBD0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LVLEN[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LVLEN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – LVLEN[15:0] Level Trigger for Corresponding Analog Input Enable bits
| Value | Description |
|---|---|
1 |
Input trigger is level-sensitive |
0 |
Input trigger is edge-sensitive |