14.3.8 ADC Control Register 4 High

Name:	ADCON4H
Offset:	0xB0E


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	C3CHS[1:0]		C2CHS[1:0]		C1CHS[1:0]		C0CHS[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – C3CHS[1:0] Dedicated ADC Core 3 Input Channel Selection bits

Value	Description
`10`	ANB3
`01`	ANA3
`00`	AN3

Bits 5:4 – C2CHS[1:0] Dedicated ADC Core 2 Input Channel Selection bits

Value	Description
`11`	ANC2
`10`	ANB2
`01`	ANA2
`00`	AN2

Bits 3:2 – C1CHS[1:0] Dedicated ADC Core 1 Input Channel Selection bits

Value	Description
`11`	ANC1
`10`	ANB1
`01`	ANA1
`00`	AN1

Bits 1:0 – C0CHS[1:0] Dedicated ADC Core 0 Input Channel Selection bits

Value	Description
`11`	ANC0
`10`	ANB0
`01`	ANA0
`00`	AN0

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