14.3.44 ADC Control Register 5 High
| Name: | ADCON5H |
| Offset: | 0xC02 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WARMTIME[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHRCIE | C3CIE | C2CIE | C1CIE | C0CIE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bits 11:8 – WARMTIME[3:0] ADC Dedicated Core Power-up Delay bits
These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC) for all ADC cores.
| Value | Description |
|---|---|
1111 |
32768 Source Clock Periods |
1110 |
16384 Source Clock Periods |
1101 |
8192 Source Clock Periods |
1100 |
4096 Source Clock Periods |
1011 |
2048 Source Clock Periods |
1010 |
1024 Source Clock Periods |
1001 |
512 Source Clock Periods |
1000 |
256 Source Clock Periods |
0111 |
128 Source Clock Periods |
0110 |
64 Source Clock Periods |
0101 |
32 Source Clock Periods |
0100 |
16 Source Clock Periods |
00xx |
16 Source Clock Periods |
Bit 7 – SHRCIE Shared ADC Core Ready Common Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common interrupt will be generated when ADC core is powered and ready for operation |
0 |
Common interrupt is disabled for an ADC core ready event |
Bit 3 – C3CIE Dedicated ADC Core 3 Ready Common Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common interrupt will be generated when ADC Core 3 is powered and ready for operation |
0 |
Common interrupt is disabled for an ADC Core 3 ready event |
Bit 2 – C2CIE Dedicated ADC Core 2 Ready Common Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common interrupt will be generated when ADC Core 2 is powered and ready for operation |
0 |
Common interrupt is disabled for an ADC Core 2 ready event |
Bit 1 – C1CIE Dedicated ADC Core 1 Ready Common Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common interrupt will be generated when ADC Core 1 is powered and ready for operation |
0 |
Common interrupt is disabled for an ADC Core 1 ready event |
Bit 0 – C0CIE Dedicated ADC Core 0 Ready Common Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Common interrupt will be generated when ADC Core 0 is powered and ready for operation |
0 |
Common interrupt is disabled for an ADC Core 0 ready event |