14.3.3 ADC Control Register 2 Low

Note:

For the 6-bit shared ADC core resolution (SHRRES[1:0] = 00), the SHREISEL[2:0] settings,  from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution  (SHRRES[1:0] = 01), the SHREISEL[2:0] settings, ‘110’ and ‘111’, are not valid and should not be used.

Name:	ADCON2L
Offset:	0xB04


Bit	15	14	13	12	11	10	9	8
	REFCIE	REFERCIE		EIEN	PTGEN	SHREISEL[2:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		SHRADCS[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 15 – REFCIE Band Gap and Reference Voltage Ready Common Interrupt Enable bit

Value	Description
`1`	Common interrupt will be generated when the band gap becomes ready
`0`	Common interrupt is disabled for the band gap ready event

Bit 14 – REFERCIE Band Gap or Reference Voltage Error Common Interrupt Enable bit

Value	Description
`1`	Common interrupt will be generated when a band gap or reference voltage error is detected
`0`	Common interrupt is disabled for the band gap and reference voltage error event

Bit 12 – EIEN Early Interrupts Enable bit

Value	Description
`1`	Early interrupt feature is enabled for input channel interrupts (when EISTATx flag is set)
`0`	Individual interrupts are generated when conversion is done (when ANxRDY flag is set)

Bit 11 – PTGEN External Conversion Request Interface bit

Setting this bit will enable the PTG to request conversion of an ADC input.

Bits 10:8 – SHREISEL[2:0] Shared Core Early Interrupt Time Selection bits⁽¹⁾

Value	Description
`111`	Early interrupt is set, interrupt is generated eight T_ADCORE clocks prior to when data are ready
`110`	Early interrupt is set, interrupt is generated seven T_ADCORE clocks prior to when data are ready
`101`	Early interrupt is set, interrupt is generated six T_ADCORE clocks prior to when data are ready
`100`	Early interrupt is set, interrupt is generated five T_ADCORE clocks prior to when the data are ready
`011`	Early interrupt is set, interrupt is generated four T_ADCORE clocks prior to when data are ready
`010`	Early interrupt is set, interrupt is generated three T_ADCORE clocks prior to when data are ready
`001`	Early interrupt is set, interrupt is generated two T_ADCORE clocks prior to when data are ready
`000`	Early interrupt is set, interrupt is generated one T_ADCORE clock prior to when data are ready

Bits 6:0 – SHRADCS[6:0] Shared ADC Core Input Clock Divider bits

These bits determine the number of T_CORESRC (Source Clock Periods) for one shared T_ADCORE (Core Clock Period).

Value	Description
`1111111`	254 Source Clock Periods
. . .
`0000011`	6 Source Clock Periods
`0000010`	4 Source Clock Periods
`0000001`	2 Source Clock Periods
`0000000`	2 Source Clock Periods

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.