Legend: n = ADC number; W = Writable bit; HC = Hardware Clearable bit; R =
Readable bit
Name:
ADnSWTRG
Offset:
0x814, 0xA14, 0xB54,
0xC74, 0xD94
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
CH[7:0]TRG
Access
W/HC/R
W/HC/R
W/HC/R
W/HC/R
W/HC/R
W/HC/R
W/HC/R
W/HC/R
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – CH[7:0]TRG Channel x Software
Trigger Request bits
A software trigger for channel
x is generated when the corresponding bit is set in this register. The software
trigger must be selected for the channel in TRG1SRC[5:0] (ADnCHxCON1[5:0]) or
TRG2SRC[5:0] (ADnCHxCON1[13:8]) bits.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.