16.3.11 ADC n Channel 0 Counter Register

Legend: n = ADC number; HS = Hardware Settable bit; HC = Hardware Clearable bit; R = Readable bit

Name:	ADnCH0CNT
Offset:	0x828, 0xA28, 0xB68, 0xC88, 0xDA8


Bit	31	30	29	28	27	26	25	24
	CNTSTAT[15:8]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CNTSTAT[7:0]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – CNTSTAT[15:0] Channel 0 Conversion Count bits

Number of conversions done in Integration (MODE[1:0] bits = ‘10’) and Window Sampling modes (MODE[1:0] bits = ‘01’).

Bits 15:0 – CNT[15:0] Channel 0 Sample Count bits

Number of samples for an Integration Sampling mode (MODE[1:0] bits = ‘10’) and maximum number of samples for a Window Sampling mode (MODE[1:0] bits = ‘01’).