16.3.8 ADC n Channel 0 Control Register 2
Legend: n = ADC number; x = Channel number; R = Readable bit; W = Writable bit
| Name: | ADnCH0CON2 |
| Offset: | 0x81C, 0xA1C, 0xB5C, 0xC7C, 0xD9C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ACCRO | ACCBRST | CMPVAL | CMPCNTMOD | ADCMPSTAT[9:8] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADCMPSTAT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMPMOD[2:0] | ADCMPCNT[9:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADCMPCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – ACCRO Accumulator Roll-Over Enable bit
| Value | Description |
|---|---|
| 1 | ADnDATAx accumulator is not cleared; it is allowed to rollover. |
| 0 | ADnDATAx accumulator is cleared at the end of a multisample. sequence |
Bit 30 – ACCBRST Oversampling Burst Mode Enable bit
| Value | Description |
|---|---|
| 1 | The oversampling performed as a continuous uninterruptible burst when all other conversion requests will be blocked out until the process is completed. |
| 0 | Oversampling can be interrupted by a high priority conversion request. |
Bit 29 – CMPVAL Comparison Value Selection bit
| Value | Description |
|---|---|
| 1 | The channel data value in ADnDATAx register is used for comparison. |
| 0 | The immediate conversion value in ADnRESx is used for comparison. |
Bit 28 – CMPCNTMOD Comparison Mode Selection bit
| Value | Description |
|---|---|
| 1 | Accumulative violation is the basis for violation count per ADCMPCNT[9:0] bits. |
| 0 | Consecutive violation is the basis for violation count per ADCMPCNT[9:0] bits. |
Bits 25:24 – ADCMPSTAT[9:8] Comparison Violation Count Status bits
The corresponding CMPxRDY bit is set when the count reaches the value set in ADCMPCNT[9:0].
Bits 23:16 – ADCMPSTAT[7:0] Comparison Violation Count Status bits
The corresponding CMPxRDY bit is set when the count reaches the value set in ADCMPCNT[9:0].
Bits 14:12 – CMPMOD[2:0] Comparison Criteria Selection bits
| Value | Description |
|---|---|
| 111-101 | Comparison is disabled. |
| 100 | Conversion result is less or equal to (≤) ADnCMPLOx register. |
| 011 | |
| 010 | Conversion result is in bounds of (≥) ADnCMPLOx and (<=) ADnCMPHIx. |
| 001 | Conversion result is out of bounds of (<) ADnCMPLOx or (>) ADnCMPHIx. |
| 000 | Comparison is disabled. |
Bits 9:0 – ADCMPCNT[9:0] Comparison Count bits
| Value | Description |
|---|---|
| 1111111111 | 1023 comparisons matching the criteria is selected. |
| 1111111110 | 1022 comparisons matching the criteria is selected. |
| ... | |
| 0000000011 | Three comparisons matching the criteria is selected. |
| 0000000010 | Two comparisons matching the criteria is selected. |
| 0000000001 | One comparison matching the criteria. |
| 0000000000 | One comparison matching the criteria. |