Legend: n = ADC number; HS = Hardware Settable bit; C = Clear Only bit; R =
Readable bit
Note: CMP[15:8]FLG bits are available on ADC5 only.
Name:
ADnCMPSTAT
Offset:
0x810, 0xA10, 0xB50,
0xC70, 0xD90
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
CMP[7:0]FLG
Access
HS/C/R
HS/C/R
HS/C/R
HS/C/R
HS/C/R
HS/C/R
HS/C/R
HS/C/R
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – CMP[7:0]FLG Channel x
Comparator Event Detection bits
These bits are set when ADC
channel data meets comparison criteria and cleared when a “0” is
written to this bit by software.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
