16.3.1 ADC n Control Register

Note:

Timing is approximate and dependent on the 32K oscillator accuracy. Changing this value during ADC operation may cause erratic recalibration timing.
Recovery from Standby mode requires 230 ADC clock cycles.
Set the ADON bit only after the ADC module has been configured. Changing ADC configuration bits when ADON = 1 will result in unpredictable behavior.

Legend: n = ADC number; HS = Hardware Settable bit; HC = Hardware Clearable bit; R = Readable bit; W = Writable bit; S = Set Only bit; C = Clear Only bit

Name:	ADnCON
Offset:	0x800, 0xA00, 0xB40, 0xC60, 0x0D80


Bit	31	30	29	28	27	26	25	24
	ADRDY	CALRDY	CALREQ	ACALEN	CALRATE[1:0]		MODE[1:0]
Access	HS/HC/R	HS/HC/R	R/W/HC	R/W	R/W	R/W	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RPTCNT[5:0]						Reserved	STNDBY
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	1	0	0	0


Bit	15	14	13	12	11	10	9	8
	ON					TSTLOCK		TSTEN
Access	R/W					R/S		R/W/C
Reset	0					0		0


Bit	7	6	5	4	3	2	1	0
	BUFEN	CALCNT[1:0]
Access	R/W	R/W	R/W
Reset	0	0	0

Bit 31 – ADRDY ADC Ready bit

The bit indicates that the ADC has been enabled and has completed its power up and self-calibration process.

Value	Description
`1`	ADC is ready.
`0`	ADC is off.

Bit 30 – CALRDY Calibration Done bit

Value	Description
`1`	Calibration cycle has finished.
`0`	Calibration was not started or is in progress.

Bit 29 – CALREQ Software Calibration Cycle Request bit

Value	Description
`1`	Setting this bit executes the calibration cycle.
`0`	Calibration cycle is not requested.

Bit 28 – ACALEN ADC Calibration Enable bit

This bit enables periodic ADC recalibration. The calibration cycles period is defined by CALRATE (ADnCON[27:26]) bits.

Value	Description
`1`	Periodic recalibration is enabled.
`0`	Periodic recalibration is off.

Bits 27:26 – CALRATE[1:0] Auto Recalibration Period bits ⁽¹⁾

Value	Description
11	Recalibration every 4096 seconds
10	Recalibrate every 1024 seconds
01	Recalibrate every 64 seconds
00	Recalibrate every second

Bits 25:24 – MODE[1:0] ADC Operation Mode Status bits

Value	Description
1x	ADC is on.
01	ADC is in Standby mode.
00	ADC is powered down.

Bits 23:18 – RPTCNT[5:0] Conversion Repeat Timer Period bits

This timer can be used to generate ADC triggers periodically by selecting the RPTCNT timer as a trigger source in TRG2SRC[5:0] (ADnCHxCON1[13:8]) bits. This timer counts ADC clock cycles.

Value	Description
111111	64 ADC clock cycles between triggers
...
0000010	Three ADC clock cycles between triggers
000001	Two ADC clock cycles between triggers
000000	One ADC clock cycle between triggers

Bit 17 – Reserved

Bit 16 – STNDBY ADC Standby Enable bit

Value	Description
1	ADC module is in a Power Reduced mode.
0	ADC is in Normal Active mode.

Bit 15 – ON ADC Enable bit⁽³⁾

Value	Description
1	ADC module is enabled.
0	ADC module is disabled.

Bit 10 – TSTLOCK TSTEN (ADnCON[8]) Lock bit

Value	Description
`1`	TSTEN bit cannot be set to `1` but can be cleared to `0`.
`0`	TSTEN bit can be set to `1`.

Bit 8 – TSTEN Test Mode Enable bit

In the Test mode the result of a conversion for all channels is overwritten with a value from ADnDATAOVR register.

Value	Description
`1`	The Test mode is enabled.
`0`	The Test mode is disabled.

Bit 7 – BUFEN Buffer Enable bit

Value	Description
1	Input Buffer is enabled.
0	Input Buffer is disabled and bypassed.

Bits 6:5 – CALCNT[1:0] ADC Idle Cycles Prior to Calibration bits

Value	Description
11	Wait for 16 activity free ADC clock cycles before initiating a requested calibration.
10	Wait for eight activity free ADC clock cycles before initiating a requested calibration.
01	Wait for four activity free ADC clock cycles before initiating a requested calibration.
00	Wait for two activity free ADC clock cycles before initiating requested calibration.