16.3.85 ADC 5 Channel 10 Control Register 1

Legend: R = Readable bit; W = Writable bit

Name:	AD5CH10CON1
Offset:	0x0ED8


Bit	31	30	29	28	27	26	25	24
	DIFF	FRAC	NINSEL[1:0]		PINSEL[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TRG1POL	EIEN	IRQSEL	SAMC[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ACCNUM[1:0]		TRG2SRC[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MODE[1:0]		TRG1SRC[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – DIFF Differential Input Enable bit

Value	Description
1	Differential Input mode; data are output as signed (two’s complement).
0	Single Ended Input mode; data are output as unsigned.

Bit 30 – FRAC Fractional Data Output Format Enable bit

Value	Description
1	Result in ADnDATAx and ADnRESx registers are aligned to the left (in the fractional format).
0	Result in ADnDATAx and ADnRESx registers are aligned to the right.

Bits 29:28 – NINSEL[1:0] Negative Analog Input Selection bits

Refer to ADC Input Availability for the available positive analog inputs.

Bits 27:24 – PINSEL[3:0] Positive Analog Input Selection bits

Refer to ADC Input Availability for the available positive analog inputs

Bit 23 – TRG1POL Starting Trigger Polarity Selection bit

Value	Description
1	Active level of the signal selected by TRG1SRC[4:0] bits is low; a falling edge generates a conversion request.
0	Active level of the signal selected by TRG1SRC[4:0] bits is high; a rising edge generates a conversion request.

Bit 22 – EIEN Early Interrupt Enable bit ⁽³⁾

Value	Description
1	Early interrupt is enabled.
0	Normal interrupt timing.

Bit 21 – IRQSEL Channel Ready Interrupt Request Select bit

Value	Description
1	The channel interrupt is generated when data are ready in the ADnDATAx register.
0	The channel interrupt is generated after each single conversion when the result is ready in ADnRESx register.

Bits 20:16 – SAMC[4:0] Sampling Time Selection bits

Value	Description
1111	62.5 T_AD
1110	60.5 T_AD
...
0010	4.5 T_AD
0001	2.5 T_AD
0000	0.5 T_AD

Bits 15:14 – ACCNUM[1:0] Oversampling Mode Number of Samples Selection bits ⁽¹⁾

Value	Description
11	256 samples, 16 bits result in ADnDATAx register
10	64 samples, 15 bits result in ADnDATAx register
01	16 samples, 14 bits result in ADnDATAx register
00	Four samples, 13 bits result in ADnDATAx register

Bits 13:8 – TRG2SRC[5:0] Multisample Conversions Re-Trigger Source Selection bits

Bits 7:6 – MODE[1:0] Sampling Mode Selection bits

Value	Description
11	Oversampling of multiple samples defined by ACCNUM[1:0] bits. The first conversion is initiated by the TRG1SRC[4:0] trigger and all other conversions are executed by the TRG2SRC[4:0] trigger.
10	Integration of multiple samples defined by: CNTx[15:0] bits (ADnCNTx[15:0]). The first conversion is initiated by the TRG1SRC[4:0] trigger and all other conversions are executed by the TRG2SRC[4:0] trigger.
01	Window gated by TRG1SRC[4:0] source. In this mode the samples are accumulated when a signal selected by the TRG1SRC[4:0] bits has an active level. All conversions are initiated by the TRG2SRC[4:0] trigger. The number of conversions is limited by CNTx[15:0] bits (ADnCNTx[15:0]).
00	Single sample initiated by the TRG1SRC[4:0] trigger.

Bits 5:0 – TRG1SRC[5:0] Multisample Conversions Re-Trigger Source Selection bits

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