Legend: n = ADC number; HS = Hardware Settable bit; HC = Hardware Clearable bit
Name:
ADnSTAT
Offset:
0x808, 0xA08, 0xB48,
0xC68, 0xD88
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
CH[7:0]RDY
Access
HS/HC
HS/HC
HS/HC
HS/HC
HS/HC
HS/HC
HS/HC
HS/HC
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – CH[7:0]RDY Channel x Data Ready
bits
Each bit in this register is set
by hardware when the corresponding channel x data is written into ADnDATAx register. The
bit is cleared by hardware when ADnDATAx register is read by
software.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
