16.3.28 ADC n Channel 3 Control Register 1

Note:
  1. These bits are used with Oversampling mode only when MODE[1:0] bits = ‘11’ and are ignored for all other sampling modes.
  2. For the correct operation, this bit must be used only for the triggers TRG1SRC[4:0] = ‘00100’ - ‘11111’.
  3. Early interrupts are only available for single sample operations (MODE[1:0] bits = ‘00’). Multi-sample operations ignore the EIEN bit and use normal interrupt timing.
  4. Do not use an early interrupt if using DMA transfers; the data might not be ready. The early interrupt is asserted at the start of sampling.

Legend: n = ADC number; R = Readable bit; W = Writable bit

Name: ADnCH3CON1
Offset: 0x878, 0xA78, 0xBB8, 0xCD8, 0xDF8

Bit 3130292827262524 
 DIFFFRACNINSEL[1:0]PINSEL[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 TRG1POLEIENIRQSELSAMC[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 ACCNUM[1:0]TRG2SRC[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 MODE[1:0]TRG1SRC[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – DIFF Differential Input Enable bit

ValueDescription
1 Differential Input mode; data are output as signed (two’s complement).
0 Single Ended Input mode; data are output as unsigned.

Bit 30 – FRAC Fractional Data Output Format Enable bit

ValueDescription
1 Result in ADnDATAx and ADnRESx registers are aligned to the left (in the fractional format).
0 Result in ADnDATAx and ADnRESx registers are aligned to the right.

Bits 29:28 – NINSEL[1:0] Negative Analog Input Selection bits

Refer to ADC Input Availability for the available positive analog inputs.

Bits 27:24 – PINSEL[3:0] Positive Analog Input Selection bits

Refer to ADC Input Availability for the available positive analog inputs

Bit 23 – TRG1POL Starting Trigger Polarity Selection bit

ValueDescription
1 Active level of the signal selected by TRG1SRC[4:0] bits, is low; a falling edge generates a conversion request.
0 Active level of the signal selected by TRG1SRC[4:0] bits is high; a rising edge generates a conversion request.

Bit 22 – EIEN  Early Interrupt Enable bit (3)

ValueDescription
1 Early interrupt is enabled.
0 Normal interrupt timing

Bit 21 – IRQSEL Channel Ready Interrupt Request Select bit

ValueDescription
1 The channel interrupt is generated when data is ready in the ADnDATAx register.
0 The channel interrupt is generated after each single conversion when result is ready in ADnRESx register.

Bits 20:16 – SAMC[4:0] Sampling Time Selection bits

ValueDescription
1111

62.5 TAD
1110

60.5 TAD
...
0010

4.5 TAD

0001

2.5 TAD
0000 0.5 TAD

Bits 15:14 – ACCNUM[1:0]  Oversampling Mode Number of Samples Selection bits (1)

ValueDescription
11 256 samples, 16 bits result in ADnDATAx register
10 64 samples, 15 bits result in ADnDATAx register
01 16 samples, 14 bits result in ADnDATAx register
00 Four samples, 13 bits result in ADnDATAx register

Bits 13:8 – TRG2SRC[5:0] Multisample Conversions Re-Trigger Source Selection bits

Bits 7:6 – MODE[1:0] Sampling Mode Selection bits

ValueDescription
11 Oversampling of multiple samples defined by ACCNUM[1:0] bits. The first conversion is initiated by the TRG1SRC[4:0] trigger and all other conversions are executed by the TRG2SRC[4:0] trigger.
10 Integration of multiple samples defined by: CNTx[15:0] bits (ADnCNTx[15:0]). The first conversion is initiated by the TRG1SRC[4:0] trigger and all other conversions are executed by the TRG2SRC[4:0] trigger.
01 Window gated by TRG1SRC[4:0] source. In this mode the samples are accumulated when a signal selected by TRG1SRC[4:0] bits has an active level. All conversions are initiated by TRG2SRC[4:0] trigger. The number of conversions is limited by CNTx[15:0] bits (ADnCNTx[15:0])
00 Single sample initiated by TRG1SRC[4:0] trigger.

Bits 5:0 – TRG1SRC[5:0] Multisample Conversions Re-Trigger Source Selection bits