5.2.7.2 LCDC Configuration Register 1
This register can only be written if WPCFGE is cleared in the LCDC Write Protection Mode Register.
GCLK must be running before writing in this register.
| Name: | LCDC_LCDCFG1 |
| Offset: | 0x00000004 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VSPW[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VSPW[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HSPW[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HSPW[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 25:16 – VSPW[9:0] Vertical Synchronization Pulse Width
Width of the LCDC_VSYNC pulse, given in number of lines. Width is (VSPW+1) lines.
Bits 9:0 – HSPW[9:0] Horizontal Synchronization Pulse Width
Width of the LCDC_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCDC_PCK cycles.